From 5c9bedf6f6e3213cd830d045d70f61de49f6e42b Mon Sep 17 00:00:00 2001 From: Srirangan Date: Thu, 23 Aug 2018 12:57:45 +0530 Subject: gpu: nvgpu: gp10b: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Ib5961506b0f95867a57f8c0d7024568785fe7b93 Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1797332 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 063bda7c..9851fc5d 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -143,8 +143,9 @@ void mc_gp10b_isr_stall(struct gk20a *g) g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { g->ops.nvlink.isr(g); } - if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) + if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) { g->ops.fb.fbpa_isr(g); + } nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); -- cgit v1.2.2