From c0fcbdf2fc853e6eaf60af131c6de1624d4d4858 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 27 Jan 2015 09:19:10 -0800 Subject: gpu: nvgpu: gp10b: Compression page size to 64k Define compression page size for gp10b to be 64k. We also need to copy some LTC initialization code from gm20b to gp10b. Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/677837 --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 95 ++++++++++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/ltc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 88f7b072..03454240 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -19,6 +19,8 @@ #include "gm20b/ltc_gm20b.h" #include "hw_ltc_gp10b.h" +#include "gk20a/ltc_common.c" + static int gp10b_determine_L2_size_bytes(struct gk20a *g) { u32 tmp; @@ -39,9 +41,98 @@ static int gp10b_determine_L2_size_bytes(struct gk20a *g) return ret; } -void gp10b_init_ltc(struct gpu_ops *gops) +static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) { - gm20b_init_ltc(gops); + /* max memory size (MB) to cover */ + u32 max_size = gr->max_comptag_mem; + /* one tag line covers 64KB */ + u32 max_comptag_lines = max_size << 4; + + u32 hw_max_comptag_lines = + ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); + + u32 cbc_param = + gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); + u32 comptags_per_cacheline = + ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); + u32 cacheline_size = + 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); + u32 slices_per_ltc = + ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); + + u32 compbit_backing_size; + + int err; + + gk20a_dbg_fn(""); + + if (max_comptag_lines == 0) { + gr->compbit_store.size = 0; + return 0; + } + + if (max_comptag_lines > hw_max_comptag_lines) + max_comptag_lines = hw_max_comptag_lines; + + compbit_backing_size = + DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * + cacheline_size * slices_per_ltc * g->ltc_count; + + /* aligned to 2KB * ltc_count */ + compbit_backing_size += + g->ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); + + /* must be a multiple of 64KB */ + compbit_backing_size = roundup(compbit_backing_size, 64*1024); + max_comptag_lines = + (compbit_backing_size * comptags_per_cacheline) / + (cacheline_size * slices_per_ltc * g->ltc_count); + + if (max_comptag_lines > hw_max_comptag_lines) + max_comptag_lines = hw_max_comptag_lines; + + gk20a_dbg_info("compbit backing store size : %d", + compbit_backing_size); + gk20a_dbg_info("max comptag lines : %d", + max_comptag_lines); + + if (tegra_platform_is_linsim()) + err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); + else + err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); + + if (err) + return err; + + gk20a_allocator_init(&gr->comp_tags, "comptag", + 1, /* start */ + max_comptag_lines - 1); /* length*/ + + gr->comptags_per_cacheline = comptags_per_cacheline; + gr->slices_per_ltc = slices_per_ltc; + gr->cacheline_size = cacheline_size; + + return 0; +} + +void gp10b_init_ltc(struct gpu_ops *gops) +{ gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; + gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; + gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; + gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; + gops->ltc.init_cbc = gk20a_ltc_init_cbc; + + /* GM20b specific ops. */ + gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; + gops->ltc.init_comptags = gp10b_ltc_init_comptags; + gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; + gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; + gops->ltc.isr = gm20b_ltc_isr; + gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; + gops->ltc.flush = gm20b_flush_ltc; +#ifdef CONFIG_DEBUG_FS + gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; +#endif } -- cgit v1.2.2