From dfdd5ba3cbc52f7359188783159b103d1d2edcf2 Mon Sep 17 00:00:00 2001 From: Ken Adams Date: Fri, 25 Jul 2014 16:47:24 -0400 Subject: gpu: nvgpu: gp10b headers first cut. just to get started... Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d Signed-off-by: Ken Adams Reviewed-on: http://git-master/r/447753 --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 385 +++++++++++++++++++++++++++++++++ 1 file changed, 385 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h new file mode 100644 index 00000000..ef53882b --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gp10b_h_ +#define _hw_ram_gp10b_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_adr_limit_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_adr_limit_lo_w(void) +{ + return 130; +} +static inline u32 ram_in_adr_limit_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_adr_limit_hi_w(void) +{ + return 131; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_gr_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_gr_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_gr_wfi_mode_physical_f(void) +{ + return 0x0; +} +static inline u32 ram_in_gr_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_gr_wfi_mode_virtual_f(void) +{ + return 0x4; +} +static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_gr_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_gr_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_semaphorea_w(void) +{ + return 14; +} +static inline u32 ram_fc_semaphoreb_w(void) +{ + return 15; +} +static inline u32 ram_fc_semaphorec_w(void) +{ + return 16; +} +static inline u32 ram_fc_semaphored_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_formats_w(void) +{ + return 39; +} +static inline u32 ram_fc_syncpointa_w(void) +{ + return 41; +} +static inline u32 ram_fc_syncpointb_w(void) +{ + return 42; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_pb_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000008; +} +#endif -- cgit v1.2.2 From 07b7a534fa8d5e93420521fcb5e745acad386f00 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 09:47:25 +0200 Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 62 +++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index ef53882b..509031e5 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,6 +78,26 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} static inline u32 ram_in_page_dir_base_lo_f(u32 v) { return (v & 0xfffff) << 12; @@ -318,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void) { return 0; } -static inline u32 ram_fc_pb_timeslice_w(void) +static inline u32 ram_fc_runlist_timeslice_w(void) { return 62; } @@ -382,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void) { return 0x00000008; } +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 ram_rl_entry_type_chid_f(void) +{ + return 0x0; +} +static inline u32 ram_rl_entry_type_tsg_f(void) +{ + return 0x2000; +} +static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 14; +} +static inline u32 ram_rl_entry_timeslice_scale_3_f(void) +{ + return 0xc000; +} +static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 18; +} +static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) +{ + return 0x2000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0x3f) << 26; +} #endif -- cgit v1.2.2 From 587a7b1e931d421b7526a0328c2c82ee78075f0c Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 8 Dec 2014 18:15:37 -0800 Subject: gpu: nvgpu: gp10b: update headers Update replayable page fault fifo, interrupt and bar2 block headers. Bug 1587825 Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/661117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 509031e5..dea53f96 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -78,6 +78,38 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} static inline u32 ram_in_big_page_size_f(u32 v) { return (v & 0x1) << 11; -- cgit v1.2.2 From fdbf60a84f4e7d0e90d0b10f5a98ef6a93b7c54e Mon Sep 17 00:00:00 2001 From: Peng Du Date: Mon, 26 Jan 2015 14:49:49 -0800 Subject: gpu: nvgpu: headers for linsim CL 34116551 Change-Id: Ia8760772b0135813475f96a786484d7caef3759d Signed-off-by: Peng Du Reviewed-on: http://git-master/r/677464 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index dea53f96..6ddff281 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,14 +78,6 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1 << 4; -} static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { return 128; @@ -94,14 +86,6 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { return 0x10; } -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1 << 5; -} static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { return 128; -- cgit v1.2.2 From 82bc7a9f2e50be7ffb99483f98b162b0a6e49765 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 20 Feb 2015 10:09:08 -0800 Subject: gpu: nvgpu: gp10b: update headers Sync with latest hw includes and generated header files. Bug 1587825 Change-Id: I165b541e3215245eb43614e34670093b8420a7df Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/709881 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 6ddff281..dea53f96 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,6 +78,14 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { return 128; @@ -86,6 +94,14 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { return 0x10; } +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { return 128; -- cgit v1.2.2 From 607b8649768ff32ce435cbf5726c9d185a68cd85 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 23 Feb 2015 15:20:36 -0800 Subject: gpu: nvgpu: Implement syncpt protection Change-Id: I05b2554588e5e1001cdbb54551cf8a064ea531bd Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/711303 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Deepak Nibade --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index dea53f96..863b15b8 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -342,6 +342,10 @@ static inline u32 ram_fc_formats_w(void) { return 39; } +static inline u32 ram_fc_allowed_syncpoints_w(void) +{ + return 58; +} static inline u32 ram_fc_syncpointa_w(void) { return 41; -- cgit v1.2.2 From ae893b37c014b13f68aa7547640bda3589363f4d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 8 Apr 2016 12:03:32 -0700 Subject: gpu: nvgpu: gp10b: Use sysmem aperture for SoC memory In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it has to be accessed as sysmem. Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1122591 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 863b15b8..55323579 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -70,6 +70,14 @@ static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) { return 0x0; } +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} static inline u32 ram_in_page_dir_base_vol_w(void) { return 128; -- cgit v1.2.2 From 528758f488a8f39c1306d8c17be4799273a94a5d Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 22 Jun 2016 16:07:46 +0530 Subject: gpu: nvgpu: Add interface for privileged channel allocation Added interface for privileged channel allocation to execute the privileged method (ex. CE phys mode transfer). JIRA DNVGPU-53 Change-Id: I1606f8c9d10f29d5a10738b5110ce9f6a2bb428d Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1169320 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 55323579..89dfbc21 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -382,6 +382,10 @@ static inline u32 ram_fc_chid_id_w(void) { return 0; } +static inline u32 ram_fc_config_w(void) +{ + return 61; +} static inline u32 ram_fc_runlist_timeslice_w(void) { return 62; -- cgit v1.2.2