From 07b7a534fa8d5e93420521fcb5e745acad386f00 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Mon, 27 Oct 2014 09:47:25 +0200
Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b

Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.

Bug 1567274

Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
---
 drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 62 +++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
index ef53882b..509031e5 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
@@ -78,6 +78,26 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void)
 {
 	return 0x4;
 }
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+	return (v & 0x1) << 11;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+	return 0x1 << 11;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+	return 0x800;
+}
 static inline u32 ram_in_page_dir_base_lo_f(u32 v)
 {
 	return (v & 0xfffff) << 12;
@@ -318,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void)
 {
 	return 0;
 }
-static inline u32 ram_fc_pb_timeslice_w(void)
+static inline u32 ram_fc_runlist_timeslice_w(void)
 {
 	return 62;
 }
@@ -382,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void)
 {
 	return 0x00000008;
 }
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+	return (v & 0x1) << 13;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+	return 0x2000;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+	return (v & 0xf) << 14;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+	return 0xc000;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+	return (v & 0xff) << 18;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+	return (v & 0x3f) << 26;
+}
 #endif
-- 
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