From dfdd5ba3cbc52f7359188783159b103d1d2edcf2 Mon Sep 17 00:00:00 2001
From: Ken Adams <kadams@nvidia.com>
Date: Fri, 25 Jul 2014 16:47:24 -0400
Subject: gpu: nvgpu: gp10b headers

first cut.  just to get started...

Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/447753
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 3173 +++++++++++++++++++++++++++++++++
 1 file changed, 3173 insertions(+)
 create mode 100644 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
new file mode 100644
index 00000000..7a4761d6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -0,0 +1,3173 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gp10b_h_
+#define _hw_gr_gp10b_h_
+
+static inline u32 gr_intr_r(void)
+{
+	return 0x00400100;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+	return 0x100000;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+	return 0x100000;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+	return 0x200000;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+	return 0x200000;
+}
+static inline u32 gr_intr_en_r(void)
+{
+	return 0x0040013c;
+}
+static inline u32 gr_exception_r(void)
+{
+	return 0x00400108;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+	return 0x1 << 24;
+}
+static inline u32 gr_exception1_r(void)
+{
+	return 0x00400118;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_exception2_r(void)
+{
+	return 0x0040011c;
+}
+static inline u32 gr_exception_en_r(void)
+{
+	return 0x00400138;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+	return 0x00400130;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+	return 0x00400134;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+	return 0x00400500;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+	return 0x10000;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+	return 0x00400704;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+	return (r >> 2) & 0xfff;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+	return (r >> 16) & 0x7;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+	return 0x00400708;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+	return 0x0040070c;
+}
+static inline u32 gr_status_r(void)
+{
+	return 0x00400700;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_status_mask_r(void)
+{
+	return 0x00400610;
+}
+static inline u32 gr_engine_status_r(void)
+{
+	return 0x0040060c;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+	return 0x00400200;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+	return 0x00400204;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+	return 0x00400208;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+	return 0x00404000;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+	return 0x00404154;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+	return 0x00404200 + i*4;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 gr_fe_tpc_fs_r(void)
+{
+	return 0x004041c4;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+	return 0x00404488;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+	return 0x0040448c;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+	return 0x00404490;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+	return 0x00404600;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+	return 0x00409100;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 gr_fecs_cpuctl_alias_r(void)
+{
+	return 0x00409130;
+}
+static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+	return 0x0040910c;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+	return 0x00409080;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+	return 0x0040904c;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+	return 0x00409040;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+	return 0x00409044;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+	return 0x00409008;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+	return 0x0040900c;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+	return 0x00409018;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+	return 0x0040901c;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+	return 0x00409050;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+	return 0x00409054;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+	return 0x004090a4;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+	return 0x00409090;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+	return 0x00409094;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+	return 0x00409200;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+	return 4;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+	return 0xe;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+	return (v & 0x1f) << 8;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+	return 0x0040920c;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+	return 0x00409180 + i*16;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+	return 0x00409184 + i*16;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+	return 0x00409188 + i*16;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+	return 0x004091c0 + i*8;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+	return 6;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+	return 0x3f << 2;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+	return (r >> 2) & 0x3f;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+	return 0x004091c4 + i*8;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+	return 0x00409110;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+	return 0x00409114;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+	return 0x0040911c;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+	return 0x00409118;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+	return 0x00409104;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+	return 0x00409108;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+	return 0x0041a108;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+	return 0x00409084;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+	return 0x00409b00;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+	return (r >> 0) & 0xfffffff;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+	return 2;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+	return (v & 0x3) << 28;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+	return 0x3 << 28;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+	return (r >> 28) & 0x3;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+	return 1;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+	return 0x00409500;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+	return 0x00409504;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+	return 0x3;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+	return 0x00000009;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+	return 0x00000015;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+	return 0x00000016;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+	return 0x00000025;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+	return 0x00000030;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+	return 0x00000031;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+	return 0x00000032;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+	return 0x00000038;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+	return 0x00000039;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+	return 0x21;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+	return 0x00409c24;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+	return 0x10000;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+	return 0x20000;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+	return 0x40000;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+	return 0x80000;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+	return 0x00409614;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+	return 0x200;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+	return 1;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+	return (v & 0x1) << 10;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+	return 0x1 << 10;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+	return (r >> 10) & 0x1;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+	return 0x400;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+	return 0x0040960c;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+	return 0x00409800 + i*4;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+	return 0x004098c0 + i*4;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+	return 0x00409840 + i*4;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+	return 0x00409604;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+	return 5;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+	return (v & 0x1f) << 0;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+	return 0x1f << 0;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+	return 5;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+	return (v & 0x1f) << 16;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+	return 0x1f << 16;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+	return (r >> 16) & 0x1f;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+	return 0x00409620;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+	return 0x00409880;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+	return 6;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+	return (v & 0x3f) << 0;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+	return 0x3f << 0;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+	return (r >> 0) & 0x3f;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+	return 0x00409400;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+	return 1;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+	return (v & 0x1) << 12;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+	return 0x1 << 12;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+	return 0x00409a24;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+	return 0x00409b04;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+	return 28;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+	return 0xfffffff << 0;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+	return (r >> 0) & 0xfffffff;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+	return 2;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+	return (v & 0x3) << 28;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+	return 0x3 << 28;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+	return (r >> 28) & 0x3;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+	return 1;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+	return 0x00409a0c;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+	return 28;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+	return 0xfffffff << 0;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+	return (r >> 0) & 0xfffffff;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+	return 2;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+	return (v & 0x3) << 28;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+	return 0x3 << 28;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+	return (r >> 28) & 0x3;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+	return 0x00409a10;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+	return 5;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+	return (v & 0x1f) << 0;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+	return 0x1f << 0;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 gr_rstr2d_gpc_map0_r(void)
+{
+	return 0x0040780c;
+}
+static inline u32 gr_rstr2d_gpc_map1_r(void)
+{
+	return 0x00407810;
+}
+static inline u32 gr_rstr2d_gpc_map2_r(void)
+{
+	return 0x00407814;
+}
+static inline u32 gr_rstr2d_gpc_map3_r(void)
+{
+	return 0x00407818;
+}
+static inline u32 gr_rstr2d_gpc_map4_r(void)
+{
+	return 0x0040781c;
+}
+static inline u32 gr_rstr2d_gpc_map5_r(void)
+{
+	return 0x00407820;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+	return 0x004078bc;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+	return 0x00406018;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+	return 0x00406028 + i*4;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+	return (v & 0xf) << 4;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+	return (v & 0xf) << 8;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+	return (v & 0xf) << 12;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+	return (v & 0xf) << 16;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+	return (v & 0xf) << 20;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+	return (v & 0xf) << 24;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+	return (v & 0xf) << 28;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+	return 0x004064c0;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+	return 0x004064c4;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+	return 0xffff;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+	return (v & 0xffff) << 16;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+	return 0x00000080;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+	return 0x004064c8;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+	return (v & 0x1fff) << 0;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+	return 0x000001c0;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+	return (v & 0x1fff) << 16;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+	return 0x00000182;
+}
+static inline u32 gr_pd_pagepool_r(void)
+{
+	return 0x004064cc;
+}
+static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_pd_pagepool_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+	return 0x004064d0 + i*4;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+	return (v & 0xff) << 16;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+	return 0x00405800;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+	return 0x00405804;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+	return 0x00405808;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+	return 0x0040580c;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+	return 0x00405810;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+	return 0x00405814;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+	return (v & 0x7f) << 0;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+	return 0x00405818;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+	return 32;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+	return 0x0040581c;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+	return 0x00405820;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+	return 0x00405824;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+	return 0x00405840;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+	return 1;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_ds_hww_esr_2_r(void)
+{
+	return 0x00405848;
+}
+static inline u32 gr_ds_hww_esr_2_reset_s(void)
+{
+	return 1;
+}
+static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 gr_ds_hww_esr_2_reset_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+	return 0x00405844;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+	return 0x100;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+	return 0x200;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+	return 0x400;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+	return 0x800;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+	return 0x1000;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+	return 0x2000;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+	return 0x4000;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+	return 0x8000;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+	return 0x10000;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+	return 0x20000;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+	return 0x40000;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+	return 0x80000;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+	return 0x100000;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+	return 0x200000;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+	return 0x400000;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+	return 0x800000;
+}
+static inline u32 gr_ds_hww_report_mask_2_r(void)
+{
+	return 0x0040584c;
+}
+static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+	return 0x00405870 + i*4;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+	return 0x00408004;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+	return 0x00408008;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+	return (v & 0x7ff) << 0;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+	return 0x00000018;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+	return 0x0040800c;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+	return 0x00408010;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+	return 0x00000080;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+	return 8;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+	return 0xff << 8;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+	return (r >> 8) & 0xff;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_scc_init_r(void)
+{
+	return 0x0040802c;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+	return 0x00408030;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+	return 0x00407020;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+	return 0x00405b00;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
+{
+	return 0x00405b60 + i*4;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
+{
+	return (v & 0xf) << 8;
+}
+static inline u32 gr_cwd_sm_id_r(u32 i)
+{
+	return 0x00405ba0 + i*4;
+}
+static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+	return 0x00502608;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+	return (r >> 16) & 0x1f;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+	return 0x00502620;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+	return 0x00502880;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+	return 6;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+	return (v & 0x3f) << 0;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+	return 0x3f << 0;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+	return (r >> 0) & 0x3f;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+	return 0x00500910;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+	return (v & 0x1ff) << 0;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+	return (v & 0xf) << 16;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+	return 0x00500914;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+	return (v & 0xf) << 8;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+	return 0x00500918;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+	return 0x00800000;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+	return 0x00500920;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+	return 0x00500a04 + i*32;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+	return 0x00000040;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+	return 0x00500c10 + i*4;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+	return 0x00500c30 + i*4;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+	return 0x00504088;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+	return 0x00504698;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+	return 0x00503018;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
+{
+	return 0x005030c0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
+{
+	return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
+{
+	return 0x3fffff << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
+{
+	return 0x00100000;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
+{
+	return 0x005030f4;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
+{
+	return 0x005030e4;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
+{
+	return 0x00000800;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
+{
+	return 0x005030f8;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+	return 0x0041a0ac;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+	return 6;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+	return (v & 0x3f) << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+	return 0x3f << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+	return (r >> 0) & 0x3f;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+	return 6;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+	return (v & 0x3f) << 6;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+	return 0x3f << 6;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+	return (r >> 6) & 0x3f;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+	return 12;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+	return 0xfff << 0;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+	return (r >> 0) & 0xfff;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+	return 0x0041a100;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+	return 0x0041a10c;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+	return 0x0041a180 + i*16;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+	return 0x0041a184 + i*16;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+	return 0x0041a188 + i*16;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+	return 0x0041a1c0 + i*8;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+	return 0x0041a1c4 + i*8;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+	return 0x0041a800 + i*4;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
+{
+	return 0x00418e24;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
+{
+	return 32;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
+{
+	return 0x00418e28;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
+{
+	return 11;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
+{
+	return (v & 0x7ff) << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
+{
+	return 0x7ff << 0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
+{
+	return (r >> 0) & 0x7ff;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
+{
+	return 0x00000018;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
+{
+	return 0x18;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
+{
+	return 1;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
+{
+	return 0x00418ea0 + i*4;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
+{
+	return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
+{
+	return 0x3fffff << 0;
+}
+static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
+{
+	return 0x00418e30;
+}
+static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+	return 0x00418810;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_crstr_gpc_map0_r(void)
+{
+	return 0x00418b08;
+}
+static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
+{
+	return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
+{
+	return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
+{
+	return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
+{
+	return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map1_r(void)
+{
+	return 0x00418b0c;
+}
+static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
+{
+	return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
+{
+	return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
+{
+	return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
+{
+	return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map2_r(void)
+{
+	return 0x00418b10;
+}
+static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
+{
+	return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
+{
+	return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
+{
+	return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
+{
+	return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map3_r(void)
+{
+	return 0x00418b14;
+}
+static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
+{
+	return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
+{
+	return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
+{
+	return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
+{
+	return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map4_r(void)
+{
+	return 0x00418b18;
+}
+static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
+{
+	return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
+{
+	return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+{
+	return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
+{
+	return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_gpc_map5_r(void)
+{
+	return 0x00418b1c;
+}
+static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+{
+	return (v & 0x7) << 5;
+}
+static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+{
+	return (v & 0x7) << 10;
+}
+static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+{
+	return (v & 0x7) << 15;
+}
+static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+{
+	return (v & 0x7) << 25;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+	return 0x00418bb8;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
+{
+	return 0x00418980;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
+{
+	return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
+{
+	return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
+{
+	return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
+{
+	return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
+{
+	return 0x00418984;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
+{
+	return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
+{
+	return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
+{
+	return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
+{
+	return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
+{
+	return 0x00418988;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
+{
+	return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
+{
+	return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
+{
+	return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
+{
+	return 3;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
+{
+	return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
+{
+	return 0x7 << 28;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
+{
+	return (r >> 28) & 0x7;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+{
+	return 0x0041898c;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+{
+	return (v & 0x7) << 4;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+{
+	return (v & 0x7) << 16;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+{
+	return (v & 0x7) << 20;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+{
+	return (v & 0x7) << 24;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+{
+	return (v & 0x7) << 28;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+	return 0x00418c6c;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+	return 0x00419004;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+	return 0x00419008;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+	return 0x0041980c;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+	return 0x00419848;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+	return (v & 0x1) << 28;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+	return 0x00419c00;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
+{
+	return 0x00419c2c;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
+{
+	return (v & 0x1) << 28;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void)
+{
+	return 0x00419e00;
+}
+static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void)
+{
+	return 0x1 << 7;
+}
+static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void)
+{
+	return 0x1 << 15;
+}
+static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void)
+{
+	return 0x8000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+{
+	return 0x00419e44;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+	return 0x100;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+	return 0x200;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
+{
+	return 0x400;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+	return 0x800;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
+{
+	return 0x1000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+	return 0x2000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+	return 0x4000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+	return 0x8000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+	return 0x10000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
+{
+	return 0x20000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+	return 0x40000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+{
+	return 0x800000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+{
+	return 0x400000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
+{
+	return 0x80000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
+{
+	return 0x100000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
+{
+	return 0x00419e4c;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+	return 0x0050450c;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void)
+{
+	return 0x00502c94;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void)
+{
+	return 0x10000;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_r(void)
+{
+	return 0x0041ac90;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void)
+{
+	return 0x00419d08;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+{
+	return 0x00504610;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+{
+	return 0x0050460c;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
+{
+	return 0x00504650;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+{
+	return 0x00504648;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+	return 0x00504770;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+	return 0x00419f70;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+	return 0x0050477c;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+	return 0x00419f7c;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void)
+{
+	return 0x00419ed8;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+	return 0x0041be08;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+{
+	return 0x0041bf00;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
+{
+	return 0x0041bf04;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
+{
+	return 0x0041bf08;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
+{
+	return 0x0041bf0c;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
+{
+	return 0x0041bf10;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
+{
+	return 0x0041bf14;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+	return 0x0041bfd0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+	return (v & 0x1f) << 16;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+	return (v & 0x7) << 21;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 24;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+	return 0x0041bfd4;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
+{
+	return 0x0041bfe4;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 0;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 5;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 10;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 15;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 20;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+{
+	return (v & 0x1f) << 25;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+	return 0x00408850;
+}
+static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_be0_crop_debug3_r(void)
+{
+	return 0x00410108;
+}
+static inline u32 gr_bes_crop_debug3_r(void)
+{
+	return 0x00408908;
+}
+static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+	return 0x00408958;
+}
+static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+	return 0x000000c0;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+	return 0x00504604;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+	return 0x00504608;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
+{
+	return 0x0050465c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
+{
+	return 0x00504660;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
+{
+	return 0x00504664;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
+{
+	return 0x00504668;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
+{
+	return 0x0050466c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
+{
+	return 0x00504658;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
+{
+	return 0x00504730;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
+{
+	return 0x00504734;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
+{
+	return 0x00504738;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
+{
+	return 0x0050473c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
+{
+	return 0x00504740;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
+{
+	return 0x00504744;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
+{
+	return 0x00504748;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
+{
+	return 0x0050474c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
+{
+	return 0x00504678;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+{
+	return 0x00504694;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
+{
+	return 0x005046f0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
+{
+	return 0x00504700;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
+{
+	return 0x005046f4;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
+{
+	return 0x00504704;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
+{
+	return 0x005046f8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
+{
+	return 0x00504708;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
+{
+	return 0x005046fc;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+{
+	return 0x0050470c;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+	return 0x00404170;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void)
+{
+	return 0x00419f88;
+}
+static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void)
+{
+	return 0x00419f80;
+}
+static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void)
+{
+	return 0x00419ccc;
+}
+static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
+{
+	return 0x00418880;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
+{
+	return 0x1 << 11;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
+{
+	return 0x3 << 3;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
+{
+	return 0x3 << 5;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
+{
+	return 0x3 << 28;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
+{
+	return 0x00418890;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
+{
+	return 0x00418894;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
+{
+	return 0x004188b0;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
+{
+	return 0x004188b4;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
+{
+	return 0x004188b8;
+}
+static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
+{
+	return 0x004188ac;
+}
+#endif
-- 
cgit v1.2.2


From badee8f41a6304817b66287e39d81b382c575163 Mon Sep 17 00:00:00 2001
From: Adeel Raza <araza@nvidia.com>
Date: Thu, 2 Oct 2014 20:39:32 -0700
Subject: gpu: nvgpu: headers for linsim CL 33688874

Bug 1561645

Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/553151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 54 ++++++++++++++++++++---------------
 1 file changed, 31 insertions(+), 23 deletions(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 7a4761d6..03164957 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1126,18 +1126,6 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
 {
 	return 0x00000182;
 }
-static inline u32 gr_pd_pagepool_r(void)
-{
-	return 0x004064cc;
-}
-static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
-{
-	return (v & 0xff) << 0;
-}
-static inline u32 gr_pd_pagepool_valid_true_f(void)
-{
-	return 0x80000000;
-}
 static inline u32 gr_pd_dist_skip_table_r(u32 i)
 {
 	return 0x004064d0 + i*4;
@@ -1302,6 +1290,18 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
 {
 	return 0x4;
 }
+static inline u32 gr_ds_tga_constraintlogic_r(void)
+{
+	return 0xffffffff;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+	return (v & 0x1) << -1;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+	return (v & 0x1) << -1;
+}
 static inline u32 gr_ds_hww_esr_r(void)
 {
 	return 0x00405840;
@@ -1536,7 +1536,7 @@ static inline u32 gr_scc_pagepool_r(void)
 }
 static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
 {
-	return (v & 0xff) << 0;
+	return (v & 0x3ff) << 0;
 }
 static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
 {
@@ -1544,7 +1544,7 @@ static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
 }
 static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
 {
-	return 0x00000080;
+	return 0x00000200;
 }
 static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
 {
@@ -1552,19 +1552,19 @@ static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
 {
-	return 8;
+	return 10;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
 {
-	return (v & 0xff) << 8;
+	return (v & 0x3ff) << 10;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
 {
-	return 0xff << 8;
+	return 0x3ff << 10;
 }
 static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
 {
-	return (r >> 8) & 0xff;
+	return (r >> 10) & 0x3ff;
 }
 static inline u32 gr_scc_pagepool_valid_true_f(void)
 {
@@ -1788,7 +1788,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
-	return 0x00100000;
+	return 0x00030000;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
 {
@@ -2068,11 +2068,19 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
 {
-	return (v & 0x3fffff) << 0;
+	return (v & 0xffffffff) << -1;
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
-	return 0x3fffff << 0;
+	return 0xffffffff << -1;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
+{
+	return (v & 0xffffffff) << -1;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void)
+{
+	return 0xffffffff << -1;
 }
 static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
 {
@@ -2080,7 +2088,7 @@ static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
 }
 static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v)
 {
-	return (v & 0xff) << 0;
+	return (v & 0x3ff) << 0;
 }
 static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void)
 {
@@ -2464,7 +2472,7 @@ static inline u32 gr_gpcs_gcc_pagepool_r(void)
 }
 static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
 {
-	return (v & 0xff) << 0;
+	return (v & 0x3ff) << 0;
 }
 static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
 {
-- 
cgit v1.2.2


From 07b7a534fa8d5e93420521fcb5e745acad386f00 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Mon, 27 Oct 2014 09:47:25 +0200
Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b

Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.

Bug 1567274

Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 228 ++++++++++++++++++++--------------
 1 file changed, 136 insertions(+), 92 deletions(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 03164957..f8607618 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -78,6 +78,26 @@ static inline u32 gr_intr_illegal_method_reset_f(void)
 {
 	return 0x10;
 }
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+	return (v & 0x1) << 8;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+	return 0x100;
+}
 static inline u32 gr_intr_illegal_class_pending_f(void)
 {
 	return 0x20;
@@ -86,6 +106,14 @@ static inline u32 gr_intr_illegal_class_reset_f(void)
 {
 	return 0x20;
 }
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+	return 0x80000;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+	return 0x80000;
+}
 static inline u32 gr_intr_class_error_pending_f(void)
 {
 	return 0x100000;
@@ -102,6 +130,26 @@ static inline u32 gr_intr_exception_reset_f(void)
 {
 	return 0x200000;
 }
+static inline u32 gr_fecs_intr_r(void)
+{
+	return 0x00400144;
+}
+static inline u32 gr_class_error_r(void)
+{
+	return 0x00400110;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+	return 0x00400120;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+	return 0x2;
+}
 static inline u32 gr_intr_en_r(void)
 {
 	return 0x0040013c;
@@ -198,6 +246,10 @@ static inline u32 gr_status_r(void)
 {
 	return 0x00400700;
 }
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
 static inline u32 gr_status_fe_method_lower_v(u32 r)
 {
 	return (r >> 2) & 0x1;
@@ -206,6 +258,10 @@ static inline u32 gr_status_fe_method_lower_idle_v(void)
 {
 	return 0x00000000;
 }
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+	return (r >> 21) & 0x1;
+}
 static inline u32 gr_status_mask_r(void)
 {
 	return 0x00400610;
@@ -662,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
 {
 	return 0x21;
 }
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+	return 0x00409c18;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+	return (v & 0x1) << 17;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+	return (v & 0x1) << 18;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+	return 0x00409c20;
+}
 static inline u32 gr_fecs_host_int_enable_r(void)
 {
 	return 0x00409c24;
@@ -1292,15 +1364,19 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
 }
 static inline u32 gr_ds_tga_constraintlogic_r(void)
 {
-	return 0xffffffff;
+	return 0x00405830;
 }
 static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
 {
-	return (v & 0x1) << -1;
+	return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_ds_tga_constraintlogic_r(void)
+{
+	return 0x0040585c;
 }
 static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
 {
-	return (v & 0x1) << -1;
+	return (v & 0xffff) << 0;
 }
 static inline u32 gr_ds_hww_esr_r(void)
 {
@@ -1674,6 +1750,34 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
 {
 	return (r >> 0) & 0x3f;
 }
+static inline u32 gr_gpccs_rc_lane_size_r(void)
+{
+	return 0x00502910;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+	return 24;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+	return 0xffffff << 0;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+	return (r >> 0) & 0xffffff;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+	return 0x0;
+}
 static inline u32 gr_gpc0_zcull_fs_r(void)
 {
 	return 0x00500910;
@@ -2068,19 +2172,11 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
 {
-	return (v & 0xffffffff) << -1;
+	return (v & 0x3fffff) << 0;
 }
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
-	return 0xffffffff << -1;
-}
-static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
-{
-	return (v & 0xffffffff) << -1;
-}
-static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void)
-{
-	return 0xffffffff << -1;
+	return 0x3fffff << 0;
 }
 static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
 {
@@ -2526,26 +2622,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
 {
 	return 0x10000000;
 }
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void)
-{
-	return 0x00419e00;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void)
-{
-	return 0x1 << 7;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void)
-{
-	return 0x80;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void)
-{
-	return 0x1 << 15;
-}
-static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void)
-{
-	return 0x8000;
-}
 static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
 {
 	return 0x00419e44;
@@ -2670,51 +2746,51 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet
 {
 	return 0x40;
 }
-static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
 {
-	return 0x0050450c;
+	return 0x00419d0c;
 }
-static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
 	return 0x2;
 }
-static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void)
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
 {
-	return 0x0;
+	return 0x0050450c;
 }
-static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void)
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
-	return 0x00502c94;
+	return 0x2;
 }
-static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void)
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
 {
-	return 0x10000;
+	return 0x0041ac94;
 }
-static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void)
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
 {
-	return 0x0;
+	return (v & 0xff) << 16;
 }
-static inline u32 gr_gpcs_gpccs_gpc_exception_r(void)
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
 {
-	return 0x0041ac90;
+	return 0x00502c90;
 }
-static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r)
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
 {
 	return (r >> 16) & 0xff;
 }
-static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void)
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
 {
 	return 0x00000001;
 }
-static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void)
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
 {
-	return 0x00419d08;
+	return 0x00504508;
 }
-static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r)
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
 {
 	return (r >> 1) & 0x1;
 }
-static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void)
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
 	return 0x00000001;
 }
@@ -2810,10 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
 {
 	return (v & 0x1) << 0;
 }
-static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void)
-{
-	return 0x00419ed8;
-}
 static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
 {
 	return 0x0041be08;
@@ -3078,42 +3150,6 @@ static inline u32 gr_fe_pwr_mode_req_done_v(void)
 {
 	return 0x00000000;
 }
-static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void)
-{
-	return 0x00419f88;
-}
-static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v)
-{
-	return (v & 0x1) << 31;
-}
-static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void)
-{
-	return 0x1 << 31;
-}
-static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void)
-{
-	return 0x00419f80;
-}
-static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v)
-{
-	return (v & 0x1) << 31;
-}
-static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void)
-{
-	return 0x1 << 31;
-}
-static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void)
-{
-	return 0x00419ccc;
-}
-static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v)
-{
-	return (v & 0x1) << 31;
-}
-static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void)
-{
-	return 0x1 << 31;
-}
 static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
 {
 	return 0x00418880;
@@ -3166,6 +3202,14 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
 {
 	return 0x004188b0;
 }
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+	return 0x00000001;
+}
 static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
 {
 	return 0x004188b4;
-- 
cgit v1.2.2


From 1e4861a347eb4ae602ff494596bacf01a6ddd4cc Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Fri, 31 Oct 2014 12:12:25 +0200
Subject: gpu: nvgpu: gp10b specific CB callbacks

Bug 1570662

Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592101
GVS: Gerrit_Virtual_Submit
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index f8607618..9b681104 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1362,7 +1362,7 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
 {
 	return 0x4;
 }
-static inline u32 gr_ds_tga_constraintlogic_r(void)
+static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
 {
 	return 0x00405830;
 }
@@ -1370,7 +1370,7 @@ static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
 {
 	return (v & 0x3fffff) << 0;
 }
-static inline u32 gr_ds_tga_constraintlogic_r(void)
+static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
 {
 	return 0x0040585c;
 }
@@ -1926,6 +1926,10 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
 {
 	return 0x005030f8;
 }
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
+{
+	return 0x005030f0;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
 	return 0x0041a0ac;
-- 
cgit v1.2.2


From 23a4456260f163881b54b89fc14ec14a2b0d1f35 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Mon, 3 Nov 2014 10:37:29 +0200
Subject: gpu: nvgpu: gp10b: Add SM debug registers

Add SM debug registers to gp10b, and regenerate headers.

Bug 1567274

Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592646
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 64 +++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 9b681104..f314c75c 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2814,6 +2814,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+{
+	return 0x40000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
 	return 0x0050460c;
@@ -2826,6 +2834,22 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
 {
 	return 0x00000001;
 }
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+{
+	return 0x00419e50;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+{
+	return 0x40;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
 {
 	return 0x00504650;
@@ -3226,4 +3250,44 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
 {
 	return 0x004188ac;
 }
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+{
+	return 0x00419e10;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+{
+	return 0x40000000;
+}
 #endif
-- 
cgit v1.2.2


From 68ad020887e93c2eb7f1bdf4fc83ec747397033a Mon Sep 17 00:00:00 2001
From: Adeel Raza <araza@nvidia.com>
Date: Wed, 5 Nov 2014 19:31:45 -0800
Subject: gpu: nvgpu: headers for linsim CL 33823014

Change-Id: I1b9172f0afa0391ce6289aa24dc1a993c723c90e
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/594681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 12 ------------
 1 file changed, 12 deletions(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index f314c75c..372c5e51 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2182,18 +2182,6 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
 	return 0x3fffff << 0;
 }
-static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
-{
-	return 0x00418e30;
-}
-static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v)
-{
-	return (v & 0x3ff) << 0;
-}
-static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void)
-{
-	return 0x80000000;
-}
 static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
 {
 	return 0x00418810;
-- 
cgit v1.2.2


From e8c5b7dd170d4bf9c49c90c4f0e8eb0e8b17c9b2 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Tue, 11 Nov 2014 11:13:41 +0200
Subject: gpu: nvgpu: Add SM registers

Add SM registers which were taken into use in GPU
characteristics.

Bug 1551769
Bug 1558186

Change-Id: I705da9ac25556b6b94137199e0acd9af3c8e6422
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601020
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 372c5e51..ca4aa6bd 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1866,6 +1866,22 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
 {
 	return (v & 0xffff) << 0;
 }
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+	return 0x0050469c;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+	return (r >> 8) & 0xfff;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
+{
+	return (r >> 20) & 0xfff;
+}
 static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
 {
 	return 0x00503018;
-- 
cgit v1.2.2


From 3cfc020b91fed07598bea39367a505a6e5bc9684 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Tue, 11 Nov 2014 13:47:03 +0200
Subject: gpu: nvgpu: Write ZBC registers to DSS

Bug 1567274

Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601108
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 48 +++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index ca4aa6bd..f2237a50 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2198,6 +2198,54 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
 {
 	return 0x3fffff << 0;
 }
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
+{
+	return 0x00418010 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
+{
+	return 0x0041804c + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
+{
+	return 0x00418088 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
+{
+	return 0x004180c4 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
+{
+	return 0x00500100;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
+{
+	return 0x00418110 + i*4;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
+{
+	return 0x0050014c;
+}
 static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
 {
 	return 0x00418810;
-- 
cgit v1.2.2


From 15839d4763e0651e789a6511476851cccef0febb Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Wed, 3 Dec 2014 16:11:50 +0200
Subject: gpu: nvgpu: Implement gp10b context creation

Implement context creation for gp10b. GfxP contexts need per channel
buffers.

Bug 1517461

Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660236
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 64 +++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index f2237a50..0bd707db 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -718,6 +718,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
 {
 	return 0x21;
 }
+static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
+{
+	return 0x0000001a;
+}
 static inline u32 gr_fecs_host_int_status_r(void)
 {
 	return 0x00409c18;
@@ -1910,6 +1914,10 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
 	return 0x00030000;
 }
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
+{
+	return 0x00030a00;
+}
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
 {
 	return 0x00000020;
@@ -2186,6 +2194,50 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
+{
+	return 0x00500ee4;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
+{
+	return 0x00000250;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
+{
+	return 0x00500ee0;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
+{
+	return 0x00418eec;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
+{
+	return 0x0041befc;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
 static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
 {
 	return 0x00418ea0 + i*4;
@@ -3342,4 +3394,16 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
 }
+static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
+{
+	return 0x004041c0;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
+{
+	return 0x0;
+}
 #endif
-- 
cgit v1.2.2


From 587a7b1e931d421b7526a0328c2c82ee78075f0c Mon Sep 17 00:00:00 2001
From: Seshendra Gadagottu <sgadagottu@nvidia.com>
Date: Mon, 8 Dec 2014 18:15:37 -0800
Subject: gpu: nvgpu: gp10b: update headers

Update replayable page fault fifo, interrupt and bar2 block
headers.

Bug 1587825

Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/661117
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 0bd707db..49078f11 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -1294,6 +1294,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
 {
 	return 0x00000004;
 }
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+	return 0x00000028;
+}
 static inline u32 gr_ds_zbc_z_r(void)
 {
 	return 0x00405818;
-- 
cgit v1.2.2


From 6cf9d594f01d9de7a602956a15c2aec6ea570b6a Mon Sep 17 00:00:00 2001
From: Deepak Nibade <dnibade@nvidia.com>
Date: Thu, 29 Jan 2015 12:20:49 +0530
Subject: gpu: nvgpu: gp10b: dump GR status registers

Add function pointer gr_gp10b_dump_gr_status_regs()
which will enable dumping GR status registers for gp10b

Bug 200062436

Change-Id: Iaecc2f9c9364232079bb03e114f68550bd035372
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/678832
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 156 ++++++++++++++++++++++++++++++++++
 1 file changed, 156 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 49078f11..a1cfab57 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -222,6 +222,10 @@ static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
 {
 	return 0x10000;
 }
+static inline u32 gr_gpfifo_status_r(void)
+{
+	return 0x00400504;
+}
 static inline u32 gr_trapped_addr_r(void)
 {
 	return 0x00400704;
@@ -266,6 +270,14 @@ static inline u32 gr_status_mask_r(void)
 {
 	return 0x00400610;
 }
+static inline u32 gr_status_1_r(void)
+{
+	return 0x00400604;
+}
+static inline u32 gr_status_2_r(void)
+{
+	return 0x00400608;
+}
 static inline u32 gr_engine_status_r(void)
 {
 	return 0x0040060c;
@@ -274,6 +286,130 @@ static inline u32 gr_engine_status_value_busy_f(void)
 {
 	return 0x1;
 }
+static inline u32 gr_activity_0_r(void)
+{
+	return 0x00400380;
+}
+static inline u32 gr_activity_1_r(void)
+{
+	return 0x00400384;
+}
+static inline u32 gr_activity_2_r(void)
+{
+	return 0x00400388;
+}
+static inline u32 gr_activity_4_r(void)
+{
+	return 0x00400390;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+	return 0x00407054;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+	return 0x00502c80;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+	return 0x00502c84;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+	return 0x00502c88;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+	return 0x00502c8c;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+	return 0x00504500;
+}
+static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
+{
+	return 0x00504d00;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+	return 0x00501d00;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+	return 0x0041ac80;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+	return 0x0041ac84;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+	return 0x0041ac88;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+	return 0x0041ac8c;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+	return 0x0041c500;
+}
+static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
+{
+	return 0x0041cd00;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+	return 0x00419d00;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+	return 0x00410200;
+}
+static inline u32 gr_pri_be1_becs_be_activity0_r(void)
+{
+	return 0x00410600;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+	return 0x00408a00;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+	return 0x00405858;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+	return 0x00404194;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+	return 0x00504238;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+	return 0x00410134;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+	return 0x00408934;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+	return 0x00410048;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+	return 0x0041004c;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+	return 0x00408848;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+	return 0x0040884c;
+}
 static inline u32 gr_pipe_bundle_address_r(void)
 {
 	return 0x00400200;
@@ -1062,6 +1198,26 @@ static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
 {
 	return (r >> 0) & 0x1f;
 }
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+	return 0x00409c00;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+	return 0x00502c04;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+	return 0x00502400;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+	return 0x00409420;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+	return 0x00502420;
+}
 static inline u32 gr_rstr2d_gpc_map0_r(void)
 {
 	return 0x0040780c;
-- 
cgit v1.2.2


From 8d717d1e7c09c9cff25d671be3cd25ea6aa57f31 Mon Sep 17 00:00:00 2001
From: Supriya <ssharatkumar@nvidia.com>
Date: Thu, 19 Feb 2015 10:40:22 +0530
Subject: gpu: nvgpu: reg with FECS HALT method

Change-Id: Ia196b98c79a71c9545e555260660e274982455a3
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/709279
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index a1cfab57..ca425447 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -858,6 +858,10 @@ static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
 {
 	return 0x0000001a;
 }
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+	return 0x00000004;
+}
 static inline u32 gr_fecs_host_int_status_r(void)
 {
 	return 0x00409c18;
-- 
cgit v1.2.2


From 3be18b463bfc7cfa66c16219e4432601ee769a26 Mon Sep 17 00:00:00 2001
From: Deepak Nibade <dnibade@nvidia.com>
Date: Mon, 2 Mar 2015 14:48:00 +0530
Subject: gpu: nvgpu: add exception registers to dump

Add below exception registers to GR dump :
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN

Bug 200078514

Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/712481
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index ca425447..3ee1cbfe 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -286,6 +286,30 @@ static inline u32 gr_engine_status_value_busy_f(void)
 {
 	return 0x1;
 }
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+	return 0x00410204;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+	return 0x00410208;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+	return 0x00502c90;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+	return 0x00502c94;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+	return 0x00504508;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+	return 0x0050450c;
+}
 static inline u32 gr_activity_0_r(void)
 {
 	return 0x00400380;
-- 
cgit v1.2.2


From 8db1d8abc2b72ecb5b1ddcbe9ff3eeaeeee072e7 Mon Sep 17 00:00:00 2001
From: Deepak Nibade <dnibade@nvidia.com>
Date: Wed, 4 Mar 2015 15:15:44 +0530
Subject: gpu: nvgpu: accessor for memfmt exception

Add accessor for NV_PGRAPH_EXCEPTION_MEMFMT

Bug 200078514

Change-Id: Ibf4ce91dfac12d7f6cffb7c65873696e080ff1a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/714167
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 3ee1cbfe..3cac1f70 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -166,6 +166,10 @@ static inline u32 gr_exception_gpc_m(void)
 {
 	return 0x1 << 24;
 }
+static inline u32 gr_exception_memfmt_m(void)
+{
+	return 0x1 << 1;
+}
 static inline u32 gr_exception1_r(void)
 {
 	return 0x00400118;
-- 
cgit v1.2.2


From d4e870edd0251cb8e8ec4915490e8716b8b67fa9 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Wed, 25 Mar 2015 10:50:41 -0700
Subject: gpu: nvgpu: gp10b: Regenerate HW headers

Change-Id: Id1954b6e96dbc75ab217a4b36a11a0457f9ceef1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/722845
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 76 +++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 3cac1f70..72f1d68c 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -170,6 +170,10 @@ static inline u32 gr_exception_memfmt_m(void)
 {
 	return 0x1 << 1;
 }
+static inline u32 gr_exception_ds_m(void)
+{
+	return 0x1 << 4;
+}
 static inline u32 gr_exception1_r(void)
 {
 	return 0x00400118;
@@ -330,6 +334,30 @@ static inline u32 gr_activity_4_r(void)
 {
 	return 0x00400390;
 }
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+	return 0x00501000;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+	return 0x00419000;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+	return 0x005046a4;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+	return 0x00419ea4;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+	return 0x1 << 0;
+}
 static inline u32 gr_pri_sked_activity_r(void)
 {
 	return 0x00407054;
@@ -3058,6 +3086,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
 {
 	return 0x0050450c;
 }
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
 	return 0x2;
@@ -3106,6 +3138,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
 {
 	return 0x00000001;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+{
+	return 0x00000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
 {
 	return 0x80000000;
@@ -3118,10 +3154,50 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
+{
+	return 0x00504614;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+{
+	return 0x00504624;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+{
+	return 0x00504634;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void)
+{
+	return 0x00000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
 	return 0x0050460c;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
 {
 	return (r >> 4) & 0x1;
-- 
cgit v1.2.2


From c258832b99468adba3cc19a38ba07234cd00de93 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Mon, 30 Mar 2015 11:21:27 -0700
Subject: gpu: nvgpu: gp10b: Correct steady state CB size

Program steady state CB size to be the HW default.

Bug 1626065

Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/725106
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 72f1d68c..02674d6b 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2174,6 +2174,14 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
 {
 	return 0x005030f0;
 }
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
+{
+	return (v & 0x3fffff) << 0;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
+{
+	return 0x00030000;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
 	return 0x0041a0ac;
-- 
cgit v1.2.2


From 0c5c1bf61ae1bd3e16a398a7b54e78314c361eb1 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Thu, 21 May 2015 08:53:53 -0700
Subject: gpu: nvgpu: gp10b: Wait for preempted or empty

ZBC is safe to update and GPU is safe to rail gate when units are
in preempted or empty state. Idle may never be reached in case of
graphics preemption, so relax the ZBC update wait condition.

Bug 1640378

Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/745655
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 02674d6b..b185604e 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -334,6 +334,30 @@ static inline u32 gr_activity_4_r(void)
 {
 	return 0x00400390;
 }
+static inline u32 gr_activity_4_gpc0_s(void)
+{
+	return 3;
+}
+static inline u32 gr_activity_4_gpc0_f(u32 v)
+{
+	return (v & 0x7) << 0;
+}
+static inline u32 gr_activity_4_gpc0_m(void)
+{
+	return 0x7 << 0;
+}
+static inline u32 gr_activity_4_gpc0_v(u32 r)
+{
+	return (r >> 0) & 0x7;
+}
+static inline u32 gr_activity_4_gpc0_empty_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_activity_4_gpc0_preempted_v(void)
+{
+	return 0x00000004;
+}
 static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
 {
 	return 0x00501000;
-- 
cgit v1.2.2


From 888a27706b1285b7482e49143ac50f8d08551d84 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Thu, 4 Jun 2015 09:17:50 -0700
Subject: gpu: nvgpu: gp10b: Program TEX RM registers

Program CB base to new gp10b registers.

Change-Id: I1ab39a487dade58d3a024fb1aba1af5c878f31bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752634
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 52 +++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index b185604e..32903fba 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2206,6 +2206,58 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
 {
 	return 0x00030000;
 }
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
+{
+	return 0x00419b00;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
+{
+	return 0x00419b04;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
+{
+	return 21;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
+{
+	return (v & 0x1fffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
+{
+	return 0x1fffff << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
+{
+	return (r >> 0) & 0x1fffff;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
+{
+	return 1;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
+{
+	return 0x80000000;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
 	return 0x0041a0ac;
-- 
cgit v1.2.2


From 910bb6ad0d326e13b16da5ee0d06f4007cc9439e Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Tue, 2 Jun 2015 20:04:18 -0700
Subject: gpu: nvgpu: gp10b: Set address check mode

Set address check mode for SM.

Bug 1625763

Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752139
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 32903fba..54d21eb3 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -3758,4 +3758,16 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
+{
+	return 0x00419c84;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
+{
+	return 0x100;
+}
 #endif
-- 
cgit v1.2.2


From 3b5a1295fa7b19296da4b370a08025d0bc6f5998 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Wed, 3 Jun 2015 15:53:12 -0700
Subject: gpu: nvgpu: gp10b: Disable RE suppression

Bug 1642669

Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755150
Reviewed-by: Automatic_Commit_Validation_User
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 54d21eb3..6e4f7d1a 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -3766,8 +3766,24 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
 {
 	return (v & 0x7) << 8;
 }
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
+{
+	return 0x7 << 8;
+}
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
 {
 	return 0x100;
 }
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
+{
+	return 0x00419f78;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
+{
+	return 0x3 << 11;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
+{
+	return 0x1000;
+}
 #endif
-- 
cgit v1.2.2


From d1331bd07d9e9b9c6432ec9406db29e197eabd8a Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Mon, 21 Sep 2015 11:10:30 -0700
Subject: gpu: nvgpu: gp10b: Implement SetCoalesceBufferSize

Implement method for setting the coalesce buffer size at runtime.

Bug 1681992

Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/802366
(cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611)
Reviewed-on: http://git-master/r/808239
GVS: Gerrit_Virtual_Submit
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 6e4f7d1a..e33f0734 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -3786,4 +3786,16 @@ static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
 {
 	return 0x1000;
 }
+static inline u32 gr_gpcs_tc_debug0_r(void)
+{
+	return 0x00418708;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
+{
+	return 0xff << 0;
+}
 #endif
-- 
cgit v1.2.2


From 959756873a2445c024df2f27c316b606a59e7e59 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Fri, 18 Sep 2015 08:16:23 -0700
Subject: gpu: nvgpu: gp10b: Fix spill buffer size

Spill buffer size is in chunks of 256B. Multiply the size by
granularity to get the size in bytes.

Bug 1686189

Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801344
(cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0)
Reviewed-on: http://git-master/r/815680
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index e33f0734..0aa68fa2 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2510,6 +2510,10 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
 {
 	return 0x00000250;
 }
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
+{
+	return 0x00000100;
+}
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
 {
 	return 0x00500ee0;
-- 
cgit v1.2.2


From 2643f200cfdb655e5ee00fa406c0dea534859df3 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Wed, 7 Oct 2015 14:52:55 -0700
Subject: gpu: nvgpu: gp10b: Use PROD value for FE_GO_IDLE_TIMEOUT

Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value
written in gk20a_init_gr_setup_hw() instead of hard coding here.

Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/813959
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 0aa68fa2..347e530d 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -538,6 +538,10 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+	return 0x7fffffff;
+}
 static inline u32 gr_fe_object_table_r(u32 i)
 {
 	return 0x00404200 + i*4;
-- 
cgit v1.2.2


From f17e0d822b47465cca23afa2054bfa1267b52b95 Mon Sep 17 00:00:00 2001
From: Adeel Raza <araza@nvidia.com>
Date: Thu, 18 Jun 2015 16:31:50 -0700
Subject: gpu: nvgpu: gp10b: add ECC support

Add ECC exception handling support for SM, TEX, and LTC.

Bug 1635727
Bug 1637486

Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935362
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 110 +++++++++++++++++++++++++++++++++-
 1 file changed, 109 insertions(+), 1 deletion(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 347e530d..9569bb9c 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -466,6 +466,70 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
 {
 	return 0x00504238;
 }
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
+{
+	return 0x005046b8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
+{
+	return 0x40;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
+{
+	return 0x200;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
+{
+	return 0x400;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
+{
+	return 0x800;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
+{
+	return 0x005044a0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
+{
+	return 0x200;
+}
 static inline u32 gr_pri_be0_crop_status1_r(void)
 {
 	return 0x00410134;
@@ -3158,6 +3222,14 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(vo
 {
 	return 0x10;
 }
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
+{
+	return 0x40000000;
+}
 static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
 {
 	return 0x20;
@@ -3174,6 +3246,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
 	return 0x2;
 }
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+	return 0x1;
+}
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
 {
 	return 0x0050450c;
@@ -3210,6 +3286,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
 {
 	return 0x00504508;
 }
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+	return 0x00000001;
+}
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
 {
 	return (r >> 1) & 0x1;
@@ -3322,6 +3406,14 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
 {
 	return 0x10;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
+{
+	return 0x40000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
 {
 	return 0x20;
@@ -3330,6 +3422,22 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(
 {
 	return 0x40;
 }
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+	return 0x00504224;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
+{
+	return 0x100;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
 	return 0x00504648;
-- 
cgit v1.2.2


From de47308b2c2ef2d24951a7e1c4ece9964417c167 Mon Sep 17 00:00:00 2001
From: Deepak Nibade <dnibade@nvidia.com>
Date: Fri, 18 Dec 2015 12:35:04 +0530
Subject: gpu: nvgpu: add CILP support for gp10b

Add CILP support for gp10b by defining below function
pointers (with detailed explanation)

pre_process_sm_exception()
- for CILP enabled channels, get the mask of errors
- if we need to broadcast the stop_trigger, suspend all SMs
- otherwise suspend only current SM
- clear hww_global_esr values in h/w
- gr_gp10b_set_cilp_preempt_pending()
  - get ctx_id
  - using sideband method, program FECS to generate
    interrupt on next ctxsw
  - disable and preempt the channel/TSG
  - set cilp_preempt_pending = true
- clear single step mode
- resume current SM

handle_fecs_error()
- we get ctxsw_intr1 upon next ctxsw
- clear this interrupt
- get handle of channel on which we first
  triggered SM exception
- gr_gp10b_clear_cilp_preempt_pending()
  - set cilp_preempt_pending = false
- send events to channel and debug session fd

Bug 200156699

Change-Id: Ia765db47e68fb968fada6409609af505c079df53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/925897
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 100 ++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 9569bb9c..b494482a 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1010,6 +1010,10 @@ static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
 {
 	return 0x00000004;
 }
+static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
+{
+	return 0x0000003a;
+}
 static inline u32 gr_fecs_host_int_status_r(void)
 {
 	return 0x00409c18;
@@ -1022,14 +1026,30 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
 {
 	return (v & 0x1) << 18;
 }
+static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
 static inline u32 gr_fecs_host_int_clear_r(void)
 {
 	return 0x00409c20;
 }
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
+{
+	return 0x2;
+}
 static inline u32 gr_fecs_host_int_enable_r(void)
 {
 	return 0x00409c24;
 }
+static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
+{
+	return 0x2;
+}
 static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
 {
 	return 0x10000;
@@ -2182,6 +2202,10 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
 {
 	return (v & 0xffff) << 0;
 }
+static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
 static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
 {
 	return 0x0050469c;
@@ -3326,6 +3350,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+	return 0x0;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
@@ -3398,6 +3430,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(
 {
 	return 0x40;
 }
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+	return 0x80000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
 {
 	return 0x00504650;
@@ -3438,6 +3490,26 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
 {
 	return 0x100;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
+{
+	return 0x80000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
 	return 0x00504648;
@@ -3454,6 +3526,22 @@ static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
+{
+	return 0x1 << 24;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
+{
+	return 0x7 << 25;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
+{
+	return 0x00504654;
+}
 static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
 {
 	return 0x00504770;
@@ -3850,6 +3938,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
+{
+	return 0x1 << 3;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
+{
+	return 0x8;
+}
+static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
+{
+	return 0x0;
+}
 static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
 {
 	return 0x1 << 30;
-- 
cgit v1.2.2


From e9b03e903c10e1fce9daf5fa7e51b8c4a0b65c95 Mon Sep 17 00:00:00 2001
From: Adeel Raza <araza@nvidia.com>
Date: Fri, 11 Dec 2015 16:16:21 -0800
Subject: gpu: nvgpu: gp10b: add ECC stats sysfs nodes

Add sysfs nodes for querying ECC single/double bit error counts.

Bug 1699676

Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 92 +++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index b494482a..0480527c 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -530,6 +530,98 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe
 {
 	return 0x200;
 }
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
+{
+	return 0x005046bc;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
+{
+	return 0x005046c0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
+{
+	return 0x005044a4;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
+{
+	return 0xff << 0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
+{
+	return 0xff << 8;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
+{
+	return (r >> 8) & 0xff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
+{
+	return 0xff << 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
+{
+	return 0x005042c4;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
+{
+	return 0x2;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
+{
+	return 0x00504218;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
+{
+	return 0xffff << 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
+{
+	return (r >> 16) & 0xffff;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
+{
+	return 0x005042ec;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
+{
+	return 0xffff << 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
+{
+	return (r >> 16) & 0xffff;
+}
 static inline u32 gr_pri_be0_crop_status1_r(void)
 {
 	return 0x00410134;
-- 
cgit v1.2.2


From 640d0e2c3b58294cd11f420a5fc8377d490c43d3 Mon Sep 17 00:00:00 2001
From: Supriya <ssharatkumar@nvidia.com>
Date: Thu, 10 Dec 2015 12:54:38 +0530
Subject: gpu: nvgpu: ECC override

-sysfs functions to call into LS PMU and modify
 ECC overide register

Bug 1699676

Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/921252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 0480527c..62ac1327 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1478,6 +1478,10 @@ static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420;
 }
+static inline u32 gr_fecs_feature_override_ecc_r(void)
+{
+	return 0x00409658;
+}
 static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
 {
 	return 0x00502420;
-- 
cgit v1.2.2


From f7872bec493d285d1f8a2c0bda69d9247f932b27 Mon Sep 17 00:00:00 2001
From: Thomas Fleury <tfleury@nvidia.com>
Date: Mon, 15 Feb 2016 11:15:19 +0100
Subject: gpu: nvpgu: setup fecs_trace hal operations

bug 1648908

Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1022730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 62ac1327..26578bb5 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1094,6 +1094,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
 {
 	return 0x21;
 }
+static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
+{
+	return 0x0000003d;
+}
 static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
 {
 	return 0x0000001a;
-- 
cgit v1.2.2


From 58adb7385de5dd3dee6d1493edbf5ee33d142dbc Mon Sep 17 00:00:00 2001
From: Sami Kiminki <skiminki@nvidia.com>
Date: Mon, 10 Aug 2015 12:06:18 +0300
Subject: gpu: nvgpu: Determine ECC-enabled units for GP10B

Determine ECC-enabled units for GP10B by reading fuses/registers.

Bug 1637486

Change-Id: I6431709e3c405d6156dd96438df14d4054b48644
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/780992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120463
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 26578bb5..b3fd704b 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1486,6 +1486,38 @@ static inline u32 gr_fecs_feature_override_ecc_r(void)
 {
 	return 0x00409658;
 }
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
+{
+	return (r >> 3) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
+{
+	return (r >> 7) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
+{
+	return (r >> 11) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
+{
+	return (r >> 8) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
 static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
 {
 	return 0x00502420;
-- 
cgit v1.2.2


From be7ee41989008b76ba118f6f520ba9b1b1efd44c Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Tue, 5 Apr 2016 19:41:01 -0700
Subject: gpu: nvgpu: gp10b: Sync with register generator

Use re-generated register definitions. This synchronizes
kernel with the register generator.

Change-Id: I5ad34ad0b92327091758a2d10581a1b4170fa919
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120811
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 64 +++++++++++++++++++++++------------
 1 file changed, 42 insertions(+), 22 deletions(-)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index b3fd704b..78792f50 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1114,6 +1114,10 @@ static inline u32 gr_fecs_host_int_status_r(void)
 {
 	return 0x00409c18;
 }
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
 static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
 {
 	return (v & 0x1) << 17;
@@ -3462,6 +3466,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 {
 	return 0x00504610;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+	return 0x1 << 0;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
 {
 	return (r >> 0) & 0x1;
@@ -3494,6 +3502,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+	return 0x1 << 1;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
 {
 	return (r >> 1) & 0x1;
@@ -3502,6 +3514,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+	return 0x1 << 2;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
 {
 	return (r >> 2) & 0x1;
@@ -3510,6 +3526,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
+{
+	return 0x00000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
 {
 	return 0x00504614;
@@ -3522,13 +3546,9 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
 {
 	return 0x00504634;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
 {
-	return 0x00000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void)
-{
-	return 0x00000000;
+	return 0x00419e24;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
@@ -3606,22 +3626,6 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(
 {
 	return 0x40;
 }
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
-{
-	return 0x00504224;
-}
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
-{
-	return 0x1;
-}
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
-{
-	return 0x80;
-}
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
-{
-	return 0x100;
-}
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
 {
 	return 0x1;
@@ -3642,6 +3646,22 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+	return 0x00504224;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
+{
+	return 0x100;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
 	return 0x00504648;
-- 
cgit v1.2.2


From ae893b37c014b13f68aa7547640bda3589363f4d Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Fri, 8 Apr 2016 12:03:32 -0700
Subject: gpu: nvgpu: gp10b: Use sysmem aperture for SoC memory

In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it
has to be accessed as sysmem.

Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1122591
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 78792f50..78304fb1 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1010,6 +1010,14 @@ static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
 static inline u32 gr_fecs_current_ctx_valid_s(void)
 {
 	return 1;
-- 
cgit v1.2.2


From a6682186de77b90fa41718d4b0012b35aba95ae0 Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Fri, 6 May 2016 15:00:17 -0700
Subject: gpu: nvgpu: gp10b: Fix CWD floorsweep programming

Program CWD TPC and SM registers correctly. The old code did not work
when there are more than 4 TPCs.

Change-Id: I18a14a0f76d97b0962607ec0bbd71aafcd768bca
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1143075
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 78304fb1..f7fd3b09 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2170,10 +2170,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
 {
 	return 0x00405b60 + i*4;
 }
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+	return 4;
+}
 static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
 {
 	return (v & 0xf) << 0;
 }
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+	return 4;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+	return (v & 0xf) << 4;
+}
 static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
 {
 	return (v & 0xf) << 8;
@@ -2182,6 +2194,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i)
 {
 	return 0x00405ba0 + i*4;
 }
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+	return 0x00000010;
+}
 static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
 {
 	return (v & 0xff) << 0;
-- 
cgit v1.2.2


From 5bc7b40524e0cd30ae5a601ed685bc2d470b8d78 Mon Sep 17 00:00:00 2001
From: Adeel Raza <araza@nvidia.com>
Date: Thu, 19 May 2016 17:24:44 -0700
Subject: gpu: nvgpu: gp10b: SM LRF ECC overcount WAR

SM LRF ECC HW overcounts errors in certain situations. Implement SW WAR
to correct error counts.

Bug 1752609
Bug 1761594

Change-Id: I79047d21e2e44e0fca3ece1da80f02faa4cd6c54
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1150773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index f7fd3b09..12d84716 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -470,6 +470,10 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
 {
 	return 0x005046b8;
 }
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b(void)
+{
+	return 4;
+}
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
 {
 	return 0x10;
@@ -486,6 +490,10 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_
 {
 	return 0x80;
 }
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b(void)
+{
+	return 8;
+}
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
 {
 	return 0x100;
-- 
cgit v1.2.2


From 943be575ccae312ab4cf10e1bdf1a2203d10d689 Mon Sep 17 00:00:00 2001
From: Adeel Raza <araza@nvidia.com>
Date: Fri, 3 Jun 2016 10:46:31 -0700
Subject: gpu: nvgpu: gp10b: clear TEX ECC interrupt

Fix bug in clearing the TEX ECC interrupt.

Bug 200206379

Change-Id: I758b55d20919173de527aeb98143851edcde4eeb
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1158806
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 12d84716..0e47c508 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -3694,6 +3694,10 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
 {
 	return 0x100;
 }
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void)
+{
+	return 0x40000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
 	return 0x00504648;
-- 
cgit v1.2.2


From b21aa660ef15dac60a011b2b1dc4a3bda6330889 Mon Sep 17 00:00:00 2001
From: Thomas Fleury <tfleury@nvidia.com>
Date: Wed, 8 Jun 2016 09:58:43 -0700
Subject: gpu: nvgpu: accessors for nv_pgraph_debug_2

Add accessors for GFXP_WFI_ALWAYS_INJECTS_WFI,
field to control FE behaviour for GFXP

Jira VFND-1900

Change-Id: Id531f795422393dc603859a0f3059d0681cf9464
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1162628
(cherry picked from commit 4175a21dd2fcbf9c25623bf5d472a3bc30476faa)
Reviewed-on: http://git-master/r/1166989
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 0e47c508..00f2ac5e 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -4162,6 +4162,26 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_debug_2_r(void)
+{
+	return 0x00400088;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void)
+{
+	return 0x1 << 23;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r)
+{
+	return (r >> 23) & 0x1;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f(void)
+{
+	return 0x800000;
+}
+static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f(void)
+{
+	return 0x0;
+}
 static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
 {
 	return 0x00419c84;
-- 
cgit v1.2.2


From bb6923908a2873b079ad67d22c9fcb014c00af28 Mon Sep 17 00:00:00 2001
From: Deepak Nibade <dnibade@nvidia.com>
Date: Tue, 6 Sep 2016 16:13:31 +0530
Subject: gpu: nvgpu: select target based on aperture

For bar2 and pmu instance blocks, use gk20a_aperture_mask()
to select target address (i.e. if address is in sysmem or
vidmem) based on aperture

Also add target accessors for gr_fecs_new_ctx and
gr_fecs_arb_ctx_ptr

Jira DNVGPU-22

Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1216138
(cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b)
Reviewed-on: http://git-master/r/1219712
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h')

diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 00f2ac5e..9e3137e7 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1414,6 +1414,14 @@ static inline u32 gr_fecs_new_ctx_target_v(u32 r)
 {
 	return (r >> 28) & 0x3;
 }
+static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
 static inline u32 gr_fecs_new_ctx_valid_s(void)
 {
 	return 1;
@@ -1466,6 +1474,14 @@ static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
 {
 	return (r >> 28) & 0x3;
 }
+static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
 static inline u32 gr_fecs_arb_ctx_cmd_r(void)
 {
 	return 0x00409a10;
-- 
cgit v1.2.2