From dfdd5ba3cbc52f7359188783159b103d1d2edcf2 Mon Sep 17 00:00:00 2001 From: Ken Adams Date: Fri, 25 Jul 2014 16:47:24 -0400 Subject: gpu: nvgpu: gp10b headers first cut. just to get started... Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d Signed-off-by: Ken Adams Reviewed-on: http://git-master/r/447753 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 1153 +++++++++++++++++++++++++++++++ 1 file changed, 1153 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h new file mode 100644 index 00000000..161c1ce0 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gp10b_h_ +#define _hw_gmmu_gp10b_h_ + +static inline u32 gmmu_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_aperture_big_video_memory_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pde_size_w(void) +{ + return 0; +} +static inline u32 gmmu_pde_size_full_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_pde_aperture_small_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_aperture_small_video_memory_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pde_vol_small_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_vol_small_true_f(void) +{ + return 0x4; +} +static inline u32 gmmu_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_vol_big_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_address_small_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_pde_address_small_sys_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pte_address_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_pte_vol_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_vol_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pte_aperture_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_pte_read_only_true_f(void) +{ + return 0x4; +} +static inline u32 gmmu_pte_write_disable_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_write_disable_true_f(void) +{ + return 0x80000000; +} +static inline u32 gmmu_pte_read_disable_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_read_disable_true_f(void) +{ + return 0x40000000; +} +static inline u32 gmmu_pte_comptagline_f(u32 v) +{ + return (v & 0x1ffff) << 12; +} +static inline u32 gmmu_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_4cz_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) +{ + return 0x0000000d; +} +static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) +{ + return 0x0000000e; +} +static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) +{ + return 0x0000000f; +} +static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +#endif -- cgit v1.2.2 From 1f3b9d851a0beb716596040f77b1431cc1fd8670 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Tue, 14 Oct 2014 18:16:32 -0700 Subject: gpu: nvgpu: headers for linsim CL 33759297 Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5 Signed-off-by: Adeel Raza --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 161c1ce0..f6020434 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x1ffff) << 12; + return (v & 0x3ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { -- cgit v1.2.2 From 07b7a534fa8d5e93420521fcb5e745acad386f00 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 09:47:25 +0200 Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index f6020434..161c1ce0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 12; + return (v & 0x1ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { -- cgit v1.2.2 From 23a4456260f163881b54b89fc14ec14a2b0d1f35 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 3 Nov 2014 10:37:29 +0200 Subject: gpu: nvgpu: gp10b: Add SM debug registers Add SM debug registers to gp10b, and regenerate headers. Bug 1567274 Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/592646 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 161c1ce0..f6020434 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x1ffff) << 12; + return (v & 0x3ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { -- cgit v1.2.2 From 1f11c7ffe745571753903fdca7024d4428bd99bd Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 13 Nov 2014 14:55:51 +0200 Subject: gpu: nvgpu: gp10b: Add new supported kind Bug 1567274 Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/606931 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index f6020434..5a0f9fe2 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -270,6 +270,26 @@ static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) { return 0x0000000b; } +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} static inline u32 gmmu_pte_kind_z16_4cz_v(void) { return 0x0000000c; @@ -1026,6 +1046,10 @@ static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) { return 0x000000e3; } +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) { return 0x000000e4; @@ -1086,6 +1110,10 @@ static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) { return 0x000000f1; } +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) { return 0x000000f2; -- cgit v1.2.2 From ac0cd782ab539d3a89ac2cc50955f80b8be456d1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 29 Jan 2015 11:29:56 -0800 Subject: gpu: nvgpu: gp10b: Implement new page table format Implement the 5-level Pascal page table format. It is enabled only for simulation. Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/682114 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 168 ++++++++++++++++++++------------ 1 file changed, 106 insertions(+), 62 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 5a0f9fe2..fc65f57d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -50,163 +50,207 @@ #ifndef _hw_gmmu_gp10b_h_ #define _hw_gmmu_gp10b_h_ -static inline u32 gmmu_pde_aperture_big_w(void) +static inline u32 gmmu_new_pde_is_pte_w(void) { return 0; } -static inline u32 gmmu_pde_aperture_big_invalid_f(void) +static inline u32 gmmu_new_pde_is_pte_false_f(void) { return 0x0; } -static inline u32 gmmu_pde_aperture_big_video_memory_f(void) +static inline u32 gmmu_new_pde_aperture_w(void) { - return 0x1; + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; } -static inline u32 gmmu_pde_size_w(void) +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) { return 0; } -static inline u32 gmmu_pde_size_full_f(void) +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) { return 0x0; } -static inline u32 gmmu_pde_address_big_sys_f(u32 v) +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { return (v & 0xfffffff) << 4; } -static inline u32 gmmu_pde_address_big_sys_w(void) +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) { return 0; } -static inline u32 gmmu_pde_aperture_small_w(void) +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) { - return 1; + return 2; } -static inline u32 gmmu_pde_aperture_small_invalid_f(void) +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) { return 0x0; } -static inline u32 gmmu_pde_aperture_small_video_memory_f(void) +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { - return 0x1; + return 0x2; } -static inline u32 gmmu_pde_vol_small_w(void) +static inline u32 gmmu_new_dual_pde_vol_small_w(void) { - return 1; + return 2; } -static inline u32 gmmu_pde_vol_small_true_f(void) +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) { - return 0x4; + return 0x8; } -static inline u32 gmmu_pde_vol_small_false_f(void) +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) { return 0x0; } -static inline u32 gmmu_pde_vol_big_w(void) +static inline u32 gmmu_new_dual_pde_vol_big_w(void) { - return 1; + return 0; } -static inline u32 gmmu_pde_vol_big_true_f(void) +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) { return 0x8; } -static inline u32 gmmu_pde_vol_big_false_f(void) +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) { return 0x0; } -static inline u32 gmmu_pde_address_small_sys_f(u32 v) +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xffffff) << 8; } -static inline u32 gmmu_pde_address_small_sys_w(void) +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { - return 1; + return 2; } -static inline u32 gmmu_pde_address_shift_v(void) +static inline u32 gmmu_new_dual_pde_address_shift_v(void) { return 0x0000000c; } -static inline u32 gmmu_pde__size_v(void) +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) { return 0x00000008; } -static inline u32 gmmu_pte__size_v(void) +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) { return 0x00000008; } -static inline u32 gmmu_pte_valid_w(void) +static inline u32 gmmu_new_pte_valid_w(void) { return 0; } -static inline u32 gmmu_pte_valid_true_f(void) +static inline u32 gmmu_new_pte_valid_true_f(void) { return 0x1; } -static inline u32 gmmu_pte_valid_false_f(void) +static inline u32 gmmu_new_pte_valid_false_f(void) { return 0x0; } -static inline u32 gmmu_pte_address_sys_f(u32 v) +static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xffffff) << 8; } -static inline u32 gmmu_pte_address_sys_w(void) +static inline u32 gmmu_new_pte_address_sys_w(void) { return 0; } -static inline u32 gmmu_pte_vol_w(void) +static inline u32 gmmu_new_pte_vol_w(void) { - return 1; + return 0; } -static inline u32 gmmu_pte_vol_true_f(void) +static inline u32 gmmu_new_pte_vol_true_f(void) { - return 0x1; + return 0x8; } -static inline u32 gmmu_pte_vol_false_f(void) +static inline u32 gmmu_new_pte_vol_false_f(void) { return 0x0; } -static inline u32 gmmu_pte_aperture_w(void) +static inline u32 gmmu_new_pte_aperture_w(void) { - return 1; + return 0; } -static inline u32 gmmu_pte_aperture_video_memory_f(void) +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { return 0x0; } -static inline u32 gmmu_pte_read_only_w(void) +static inline u32 gmmu_new_pte_read_only_w(void) { return 0; } -static inline u32 gmmu_pte_read_only_true_f(void) +static inline u32 gmmu_new_pte_read_only_true_f(void) { - return 0x4; + return 0x40; } -static inline u32 gmmu_pte_write_disable_w(void) +static inline u32 gmmu_new_pte_comptagline_f(u32 v) { - return 1; + return (v & 0x3ffff) << 4; } -static inline u32 gmmu_pte_write_disable_true_f(void) -{ - return 0x80000000; -} -static inline u32 gmmu_pte_read_disable_w(void) +static inline u32 gmmu_new_pte_comptagline_w(void) { return 1; } -static inline u32 gmmu_pte_read_disable_true_f(void) -{ - return 0x40000000; -} -static inline u32 gmmu_pte_comptagline_f(u32 v) +static inline u32 gmmu_new_pte_kind_f(u32 v) { - return (v & 0x3ffff) << 12; + return (v & 0xff) << 24; } -static inline u32 gmmu_pte_comptagline_w(void) +static inline u32 gmmu_new_pte_kind_w(void) { return 1; } -static inline u32 gmmu_pte_address_shift_v(void) +static inline u32 gmmu_new_pte_address_shift_v(void) { return 0x0000000c; } -- cgit v1.2.2 From 94a7c5ff2cbe8a583e9b8fc4777e5debe4c48810 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 26 May 2015 16:12:19 -0700 Subject: gpu: nvgpu: gp10b: Fix PDE/PTE address handling We were dropping the part of address that span word bounary. The register generator does not know how to real with multi-word fields, to edit things in manually. Bug 1646531 Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/747468 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index fc65f57d..844cb142 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -72,7 +72,7 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void) } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_pde_address_sys_w(void) { @@ -164,7 +164,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { @@ -200,7 +200,7 @@ static inline u32 gmmu_new_pte_valid_false_f(void) } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_pte_address_sys_w(void) { -- cgit v1.2.2 From 6a071e5ad5581e57a5be109d2fc0f44680207783 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 24 Jun 2015 10:10:57 -0700 Subject: gpu: nvgpu: gp10b: Implement priv pages Implement support for privileged pages. Use them for kernel allocated buffers. Change-Id: I24778c2b6063b6bc8a4bfd9d97fa6de01d49569a Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/761920 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 844cb142..9ce9448e 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -198,6 +198,18 @@ static inline u32 gmmu_new_pte_valid_false_f(void) { return 0x0; } +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} static inline u32 gmmu_new_pte_address_sys_f(u32 v) { return (v & 0xfffffff) << 8; -- cgit v1.2.2 From be7ee41989008b76ba118f6f520ba9b1b1efd44c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 5 Apr 2016 19:41:01 -0700 Subject: gpu: nvgpu: gp10b: Sync with register generator Use re-generated register definitions. This synchronizes kernel with the register generator. Change-Id: I5ad34ad0b92327091758a2d10581a1b4170fa919 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1120811 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 9ce9448e..30e4307d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, -- cgit v1.2.2 From ae893b37c014b13f68aa7547640bda3589363f4d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 8 Apr 2016 12:03:32 -0700 Subject: gpu: nvgpu: gp10b: Use sysmem aperture for SoC memory In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it has to be accessed as sysmem. Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1122591 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 30e4307d..86870aea 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -70,6 +70,14 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void) { return 0x2; } +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_pde_address_sys_f(u32 v) { return (v & 0xfffffff) << 8; @@ -118,6 +126,14 @@ static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) { return 0x2; } +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { return (v & 0xfffffff) << 4; @@ -138,6 +154,14 @@ static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { return 0x2; } +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_dual_pde_vol_small_w(void) { return 2; @@ -238,6 +262,14 @@ static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { return 0x0; } +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_pte_read_only_w(void) { return 0; -- cgit v1.2.2 From d6730d5214a941451a298a22a037e5bcc4fb9ea4 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Fri, 17 Jun 2016 15:45:31 +0300 Subject: gpu: nvgpu: gp10x: add support for vidmem in page tables Modify page table updates to take an aperture flag (up until gk20a_locked_gmmu_map()), don't hard-assume sysmem and propagate it to hardware. Jira DNVGPU-76 Change-Id: I797fdaaf5f42a84fa0446577359147fb6908a720 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1169295 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 86870aea..d231ee44 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void) { return 0; } +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} static inline u32 gmmu_new_pte_vol_w(void) { return 0; -- cgit v1.2.2