From 16c511220ecda4a0220976f649fddabcfbee86e0 Mon Sep 17 00:00:00 2001 From: Kenneth Adams Date: Wed, 1 Oct 2014 08:27:17 -0700 Subject: gpu: nvgpu: t18x, gp10b framework This change adds gp10b to the nvgpu build as well as enabling CMA for buffer allocation. Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76 Signed-off-by: Ken Adams Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/553324 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 98 +++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/hal_gp10b.c (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c new file mode 100644 index 00000000..61bae5c7 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -0,0 +1,98 @@ +/* + * GP10B Tegra HAL interface + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include + +#include "gk20a/gk20a.h" + +#include "gp10b/gr_gp10b.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/fb_gm20b.h" +#include "gm20b/gm20b_gating_reglist.h" +#include "gm20b/fifo_gm20b.h" +#include "gm20b/gr_ctx_gm20b.h" +#include "gm20b/mm_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/clk_gm20b.h" + +struct gpu_ops gp10b_ops = { + .clock_gating = { + .slcg_bus_load_gating_prod = + gm20b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gm20b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gm20b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gm20b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gm20b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gm20b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gm20b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gm20b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gm20b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gm20b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gm20b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gm20b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gm20b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gm20b_blcg_bus_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gm20b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gm20b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gm20b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gm20b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gm20b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gm20b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gm20b_blcg_pmu_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gm20b_pg_gr_load_gating_prod, + } +}; + +int gp10b_init_hal(struct gpu_ops *gops) +{ + *gops = gp10b_ops; + gm20b_init_ltc(gops); + gp10b_init_gr(gops); + gm20b_init_ltc(gops); + gm20b_init_fb(gops); + gm20b_init_fifo(gops); + gm20b_init_gr_ctx(gops); + gm20b_init_mm(gops); + gm20b_init_pmu_ops(gops); + gm20b_init_clk_ops(gops); + gops->name = "gp10b"; + + return 0; +} -- cgit v1.2.2 From 0b50f2a2020c81f00999a8f06a67dde4c214821f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 15:05:45 +0200 Subject: gpu: nvgpu: Implement gp10b intr processing Bug 1567274 Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/591628 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 61bae5c7..235254c8 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gp10b/gr_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/fb_gm20b.h" @@ -83,6 +84,7 @@ struct gpu_ops gp10b_ops = { int gp10b_init_hal(struct gpu_ops *gops) { *gops = gp10b_ops; + gp10b_init_mc(gops); gm20b_init_ltc(gops); gp10b_init_gr(gops); gm20b_init_ltc(gops); -- cgit v1.2.2 From 317e7bb75862eb7e7272271435a6387a4f5c9839 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 5 Nov 2014 11:21:03 +0200 Subject: gpu: nvgpu: gp10b: Fill class numbers Fill class numbers to characteristics structure. Bug 1567274 Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/594404 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 235254c8..067c9bf4 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -23,6 +23,7 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/mc_gp10b.h" +#include "gm20b/gr_gm20b.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" @@ -81,8 +82,11 @@ struct gpu_ops gp10b_ops = { } }; -int gp10b_init_hal(struct gpu_ops *gops) +int gp10b_init_hal(struct gk20a *g) { + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + *gops = gp10b_ops; gp10b_init_mc(gops); gm20b_init_ltc(gops); @@ -96,5 +100,12 @@ int gp10b_init_hal(struct gpu_ops *gops) gm20b_init_clk_ops(gops); gops->name = "gp10b"; + c->twod_class = FERMI_TWOD_A; + c->threed_class = PASCAL_A; + c->compute_class = PASCAL_COMPUTE_A; + c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = MAXWELL_DMA_COPY_A; + return 0; } -- cgit v1.2.2 From 7918de1c1b05ae126f830588de1cac533ef1c0cf Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 13 Nov 2014 13:30:52 +0200 Subject: gpu: nvgpu: gp10b: Implement L2 query Bug 1567274 Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/602858 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 067c9bf4..5ef64e1f 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -22,9 +22,9 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/mc_gp10b.h" +#include "gp10b/ltc_gp10b.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/ltc_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" @@ -89,9 +89,8 @@ int gp10b_init_hal(struct gk20a *g) *gops = gp10b_ops; gp10b_init_mc(gops); - gm20b_init_ltc(gops); gp10b_init_gr(gops); - gm20b_init_ltc(gops); + gp10b_init_ltc(gops); gm20b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); -- cgit v1.2.2 From c23f7708ac84c1866b2d9f1b8d5a9e560026e859 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 12 Nov 2014 14:32:29 +0200 Subject: gpu: nvgpu: gp10b: Define physical address width GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601703 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 5ef64e1f..acd1b73c 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -23,13 +23,13 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/gr_ctx_gm20b.h" -#include "gm20b/mm_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" @@ -94,7 +94,7 @@ int gp10b_init_hal(struct gk20a *g) gm20b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); - gm20b_init_mm(gops); + gp10b_init_mm(gops); gm20b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); gops->name = "gp10b"; -- cgit v1.2.2 From 1f11c7ffe745571753903fdca7024d4428bd99bd Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 13 Nov 2014 14:55:51 +0200 Subject: gpu: nvgpu: gp10b: Add new supported kind Bug 1567274 Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/606931 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index acd1b73c..a739ce77 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -24,9 +24,9 @@ #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/fb_gp10b.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/gr_ctx_gm20b.h" @@ -91,7 +91,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mc(gops); gp10b_init_gr(gops); gp10b_init_ltc(gops); - gm20b_init_fb(gops); + gp10b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); gp10b_init_mm(gops); -- cgit v1.2.2 From 5452d161544f40778f75dda06bfddb14bcb48707 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 11 Dec 2014 12:40:03 +0530 Subject: gpu: nvgpu: gp10b: gpmu elpg support Temporally used gm20b elpg sequencing values for gp10b elpg. Bug 1525971 Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/662517 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a739ce77..526caff1 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -25,6 +25,7 @@ #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/pmu_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" @@ -95,7 +96,7 @@ int gp10b_init_hal(struct gk20a *g) gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); gp10b_init_mm(gops); - gm20b_init_pmu_ops(gops); + gp10b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); gops->name = "gp10b"; -- cgit v1.2.2 From 667143ed939494f311ba45e3cfd89546e625bbca Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 22 Jan 2015 08:02:21 -0800 Subject: gpu: nvgpu: gp10b: Enable cycling through ctx bins Remove hard coded NETB for gp10b. This enables cycling through available firmware files. Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/676557 Reviewed-by: Peng Du GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 526caff1..161c20c6 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -26,11 +26,11 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gp10b/gr_ctx_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" -#include "gm20b/gr_ctx_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" @@ -94,7 +94,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_ltc(gops); gp10b_init_fb(gops); gm20b_init_fifo(gops); - gm20b_init_gr_ctx(gops); + gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); -- cgit v1.2.2 From ea29b9e779ebbc7ab5fc9daa2dc4ebcde63b3550 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 30 Jan 2015 15:14:55 -0800 Subject: gpu: nvgpu: gp10b: Enable debug spew Change-Id: I58811bbce0e39b85074f3aa9022a730f696e407e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/679704 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 161c20c6..1a34688a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -98,6 +98,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); + gk20a_init_debug_ops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From eff1aa4d9212f76f24d362bc1f871bf82baa5d98 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 16 Jan 2015 09:15:20 -0800 Subject: gpu: nvgpu: gp10b: Set correct PBDMA signature GPFIFO class was set to Maxwell class number. Also implement the PBDMA signature HAL. Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/672921 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 1a34688a..30b56a5c 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -31,6 +31,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" +#include "gp10b/fifo_gp10b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" @@ -93,7 +94,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gm20b_init_fifo(gops); + gp10b_init_fifo(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); @@ -104,7 +105,7 @@ int gp10b_init_hal(struct gk20a *g) c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; c->compute_class = PASCAL_COMPUTE_A; - c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A; + c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A; c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; c->dma_copy_class = MAXWELL_DMA_COPY_A; -- cgit v1.2.2 From 20a1ab078546c7206bb65ab007882195953df1dd Mon Sep 17 00:00:00 2001 From: Sam Payne Date: Thu, 5 Feb 2015 10:46:35 -0800 Subject: gpu: nvgpu: gp10b: add ce interrupt support ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 30b56a5c..c23c0f17 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,7 @@ #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/ce2_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" @@ -94,7 +95,8 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gp10b_init_fifo(gops); + gm20b_init_fifo(gops); + gp10b_init_ce2(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); -- cgit v1.2.2 From 750014be79cce9562653db96e735f78fdc2e058f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 5 Feb 2015 14:01:59 -0800 Subject: gpu: nvgpu: gp10b: support for replayable faults Add support for enabling replayable faults during channel instance block binding. Also fixed register programing sequence for setting channel pbdma timeout. Bug 1587825 Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/681703 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index c23c0f17..ff140a04 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -28,6 +28,7 @@ #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" +#include "gp10b/fifo_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" @@ -95,7 +96,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gm20b_init_fifo(gops); + gp10b_init_fifo(gops); gp10b_init_ce2(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); -- cgit v1.2.2 From 0158c380376722636ff696543071427ef3d3739f Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 6 Apr 2015 16:32:29 +0530 Subject: gpu: nvgpu: gp10b: fix sparse warnings of static symbol Fix sparse warnings of below type by making necessary symbols static: warning: symbol '' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index ff140a04..31597753 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -37,7 +37,7 @@ #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" -struct gpu_ops gp10b_ops = { +static struct gpu_ops gp10b_ops = { .clock_gating = { .slcg_bus_load_gating_prod = gm20b_slcg_bus_load_gating_prod, -- cgit v1.2.2 From 0f2a1edd655be0d6f364c07a409ee100ca940f4b Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 8 Apr 2015 23:06:11 +0530 Subject: gpu: nvgpu: secure boot flag, default disabled - set "privsecurity" to 1 to enable secure boot else set to 0. Bug 200085428 Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/729101 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Tested-by: Vijayakumar Subbu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 31597753..914d8089 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -92,6 +92,8 @@ int gp10b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; *gops = gp10b_ops; + gops->privsecurity = 0; + gp10b_init_mc(gops); gp10b_init_gr(gops); gp10b_init_ltc(gops); -- cgit v1.2.2 From 93e001d24f9ee31bf4f0810e9aa91e70df992cc5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 27 Mar 2015 09:09:54 -0700 Subject: gpu: nvgpu: gp10b: Gating reglist Change-Id: I4931958c21692306d6c78bffdc45e21c553b913c Signed-off-by: Terje Bergstrom Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/731494 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 47 +++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 25 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 914d8089..9d099479 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -29,60 +29,57 @@ #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" #include "gp10b/fifo_gp10b.h" +#include "gp10b/gp10b_gating_reglist.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" -#include "gp10b/fifo_gp10b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" static struct gpu_ops gp10b_ops = { .clock_gating = { .slcg_bus_load_gating_prod = - gm20b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gm20b_slcg_ce2_load_gating_prod, + gp10b_slcg_bus_load_gating_prod, .slcg_chiplet_load_gating_prod = - gm20b_slcg_chiplet_load_gating_prod, + gp10b_slcg_chiplet_load_gating_prod, .slcg_ctxsw_firmware_load_gating_prod = - gm20b_slcg_ctxsw_firmware_load_gating_prod, + gp10b_slcg_ctxsw_firmware_load_gating_prod, .slcg_fb_load_gating_prod = - gm20b_slcg_fb_load_gating_prod, + gp10b_slcg_fb_load_gating_prod, .slcg_fifo_load_gating_prod = - gm20b_slcg_fifo_load_gating_prod, + gp10b_slcg_fifo_load_gating_prod, .slcg_gr_load_gating_prod = - gr_gm20b_slcg_gr_load_gating_prod, + gr_gp10b_slcg_gr_load_gating_prod, .slcg_ltc_load_gating_prod = - ltc_gm20b_slcg_ltc_load_gating_prod, + ltc_gp10b_slcg_ltc_load_gating_prod, .slcg_perf_load_gating_prod = - gm20b_slcg_perf_load_gating_prod, + gp10b_slcg_perf_load_gating_prod, .slcg_priring_load_gating_prod = - gm20b_slcg_priring_load_gating_prod, + gp10b_slcg_priring_load_gating_prod, .slcg_pmu_load_gating_prod = - gm20b_slcg_pmu_load_gating_prod, + gp10b_slcg_pmu_load_gating_prod, .slcg_therm_load_gating_prod = - gm20b_slcg_therm_load_gating_prod, + gp10b_slcg_therm_load_gating_prod, .slcg_xbar_load_gating_prod = - gm20b_slcg_xbar_load_gating_prod, + gp10b_slcg_xbar_load_gating_prod, .blcg_bus_load_gating_prod = - gm20b_blcg_bus_load_gating_prod, + gp10b_blcg_bus_load_gating_prod, .blcg_ctxsw_firmware_load_gating_prod = - gm20b_blcg_ctxsw_firmware_load_gating_prod, + gp10b_blcg_ctxsw_firmware_load_gating_prod, .blcg_fb_load_gating_prod = - gm20b_blcg_fb_load_gating_prod, + gp10b_blcg_fb_load_gating_prod, .blcg_fifo_load_gating_prod = - gm20b_blcg_fifo_load_gating_prod, + gp10b_blcg_fifo_load_gating_prod, .blcg_gr_load_gating_prod = - gm20b_blcg_gr_load_gating_prod, + gp10b_blcg_gr_load_gating_prod, .blcg_ltc_load_gating_prod = - gm20b_blcg_ltc_load_gating_prod, + gp10b_blcg_ltc_load_gating_prod, .blcg_pwr_csb_load_gating_prod = - gm20b_blcg_pwr_csb_load_gating_prod, + gp10b_blcg_pwr_csb_load_gating_prod, .blcg_pmu_load_gating_prod = - gm20b_blcg_pmu_load_gating_prod, + gp10b_blcg_pmu_load_gating_prod, .pg_gr_load_gating_prod = - gr_gm20b_pg_gr_load_gating_prod, + gr_gp10b_pg_gr_load_gating_prod, } }; -- cgit v1.2.2 From a22aa6d4d338f9d8fc126c4062c416b74785d728 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 22 Jun 2015 12:42:23 -0700 Subject: gpu: nvgpu: gp10b: Do not set up gm20b clocks gm20b clock registers do not exist in gp10b. Skip setting the clock HAL to gm20b variants. Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/760854 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9d099479..d50ad791 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -100,7 +100,6 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); - gm20b_init_clk_ops(gops); gk20a_init_debug_ops(gops); gops->name = "gp10b"; -- cgit v1.2.2 From 4b806879d582d41b20c17cc1739b537dbd41cb9a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 22 Jun 2015 16:19:44 -0700 Subject: gpu: nvgpu: gp10b: Add regops whitelists Add regops whitelists for gp10b. The whitelist is generated, and is the same for context switched and global registers. Bug 1633363 Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/760935 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d50ad791..9eba5571 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -30,6 +30,7 @@ #include "gp10b/gr_ctx_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/gp10b_gating_reglist.h" +#include "gp10b/regops_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -101,6 +102,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); + gp10b_init_regops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 95a271905918d91468134728079c3025ea58b537 Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Tue, 18 Aug 2015 19:34:51 +0300 Subject: gpu: nvgpu: Add CDE program number selection for GP10B Add CDE program number selection for GP10B. Bug 1604102 Change-Id: I0054e670e3bc6b8c2380124eb58204088aaae275 Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/785459 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9eba5571..983b985d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -31,6 +31,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/gp10b_gating_reglist.h" #include "gp10b/regops_gp10b.h" +#include "gp10b/cde_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -103,6 +104,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gp10b_init_regops(gops); + gp10b_init_cde_ops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 71afbe484f0bda343f73c3afcfd5ca4205be4e09 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sat, 29 Aug 2015 05:12:29 +0530 Subject: gpu: nvgpu: fuse read to boot in SECURE mode -Read fuse to boot in secure/production mode else non sercure mode. Bug N/A Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/791323 Reviewed-on: http://git-master/r/806191 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 39 ++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 983b985d..a6131cea 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -37,6 +37,10 @@ #include "gm20b/fifo_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" +#include + +#define FUSE_OPT_PRIV_SEC_EN_0 0x264 +#define PRIV_SECURITY_ENABLED 0x01 static struct gpu_ops gp10b_ops = { .clock_gating = { @@ -91,7 +95,40 @@ int gp10b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; *gops = gp10b_ops; - gops->privsecurity = 0; + +#ifdef CONFIG_TEGRA_ACR + if (tegra_platform_is_linsim()) { + gops->privsecurity = 1; + gops->securegpccs = 1; + } else { + if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & + PRIV_SECURITY_ENABLED) { + gops->privsecurity = 1; + gops->securegpccs =1; + } else { + gk20a_dbg_info("priv security is disabled in HW"); + gops->privsecurity = 0; + gops->securegpccs = 0; + } + } +#else + if (tegra_platform_is_linsim()) { + gk20a_dbg_info("running ASIM with PRIV security disabled"); + gops->privsecurity = 0; + gops->securegpccs = 0; + } else { + if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & + PRIV_SECURITY_ENABLED) { + gk20a_dbg_info("priv security is not supported but enabled"); + gops->privsecurity = 1; + gops->securegpccs =1; + return -EPERM; + } else { + gops->privsecurity = 0; + gops->securegpccs = 0; + } + } +#endif gp10b_init_mc(gops); gp10b_init_gr(gops); -- cgit v1.2.2 From 8e1c56689639917ca637875434a074fb697435e8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 20 Sep 2015 13:36:54 -0700 Subject: gpu: nvgpu: gp10b: Always disable security in sim Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/801850 Reviewed-on: http://git-master/r/806192 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a6131cea..70486c4a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -98,8 +98,8 @@ int gp10b_init_hal(struct gk20a *g) #ifdef CONFIG_TEGRA_ACR if (tegra_platform_is_linsim()) { - gops->privsecurity = 1; - gops->securegpccs = 1; + gops->privsecurity = 0; + gops->securegpccs = 0; } else { if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & PRIV_SECURITY_ENABLED) { -- cgit v1.2.2 From 9fb5c25782af6ef1e4a60056afbce7a7e1bff46c Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 25 Sep 2015 17:32:29 -0700 Subject: gpu: nvgpu: gp10b: update slcg xbar prod settings Bug 1689806 Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/806115 (cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd) Reviewed-on: http://git-master/r/805482 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 70486c4a..381ee8b1 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -84,6 +84,8 @@ static struct gpu_ops gp10b_ops = { gp10b_blcg_pwr_csb_load_gating_prod, .blcg_pmu_load_gating_prod = gp10b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gp10b_blcg_xbar_load_gating_prod, .pg_gr_load_gating_prod = gr_gp10b_pg_gr_load_gating_prod, } -- cgit v1.2.2 From 4d3f44849bd48f1a2390692ccce7e7203d3198ae Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 1 Oct 2015 10:38:32 -0700 Subject: gpu: nvgpu: gp10b: Report Pascal DMA copy class Announce supporting Pascal DMA copy class instead of Maxwell. Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/808140 (cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7) Reviewed-on: http://git-master/r/815679 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 381ee8b1..5222fca6 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -151,7 +151,7 @@ int gp10b_init_hal(struct gk20a *g) c->compute_class = PASCAL_COMPUTE_A; c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A; c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = MAXWELL_DMA_COPY_A; + c->dma_copy_class = PASCAL_DMA_COPY_A; return 0; } -- cgit v1.2.2 From 313fcdb1d3c12026246df01c81e2ecd212132de8 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 22 Oct 2015 15:31:43 -0700 Subject: gpu: nvgpu: gp10b: update thermal programming Add required fileds and values for thermal slow-down settings in thermal header file and corrected thermal register programming with correct values. Bug 1695567 Reviewed-on: http://git-master/r/822200 (cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981) Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/823013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 5222fca6..544be96b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -32,6 +32,7 @@ #include "gp10b/gp10b_gating_reglist.h" #include "gp10b/regops_gp10b.h" #include "gp10b/cde_gp10b.h" +#include "gp10b/therm_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -144,6 +145,7 @@ int gp10b_init_hal(struct gk20a *g) gk20a_init_debug_ops(gops); gp10b_init_regops(gops); gp10b_init_cde_ops(gops); + gp10b_init_therm_ops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 57a75c3ba632a0300b932ce574ea3caab8275f4c Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 14 Mar 2016 12:00:05 -0700 Subject: gpu: nvgpu: gp10b: update prod setiings Add/update following prod settings: blcg ce slcg ce2 Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1030986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 544be96b..37fad41a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -47,6 +47,8 @@ static struct gpu_ops gp10b_ops = { .clock_gating = { .slcg_bus_load_gating_prod = gp10b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gp10b_slcg_ce2_load_gating_prod, .slcg_chiplet_load_gating_prod = gp10b_slcg_chiplet_load_gating_prod, .slcg_ctxsw_firmware_load_gating_prod = @@ -71,6 +73,8 @@ static struct gpu_ops gp10b_ops = { gp10b_slcg_xbar_load_gating_prod, .blcg_bus_load_gating_prod = gp10b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gp10b_blcg_ce_load_gating_prod, .blcg_ctxsw_firmware_load_gating_prod = gp10b_blcg_ctxsw_firmware_load_gating_prod, .blcg_fb_load_gating_prod = -- cgit v1.2.2 From f7872bec493d285d1f8a2c0bda69d9247f932b27 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 15 Feb 2016 11:15:19 +0100 Subject: gpu: nvpgu: setup fecs_trace hal operations bug 1648908 Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1022730 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 37fad41a..4f67cb09 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gp10b/gr_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" @@ -139,6 +140,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mc(gops); gp10b_init_gr(gops); + gp10b_init_fecs_trace_ops(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); gp10b_init_fifo(gops); -- cgit v1.2.2 From 58adb7385de5dd3dee6d1493edbf5ee33d142dbc Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 10 Aug 2015 12:06:18 +0300 Subject: gpu: nvgpu: Determine ECC-enabled units for GP10B Determine ECC-enabled units for GP10B by reading fuses/registers. Bug 1637486 Change-Id: I6431709e3c405d6156dd96438df14d4054b48644 Signed-off-by: Sami Kiminki Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/780992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-on: http://git-master/r/1120463 Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 4f67cb09..427936c7 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -41,6 +41,8 @@ #include "gm20b/clk_gm20b.h" #include +#include "gp10b.h" + #define FUSE_OPT_PRIV_SEC_EN_0 0x264 #define PRIV_SECURITY_ENABLED 0x01 @@ -153,6 +155,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_cde_ops(gops); gp10b_init_therm_ops(gops); gops->name = "gp10b"; + gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; -- cgit v1.2.2 From 342d45e060ba9c6a7815633c351ec8d95422dcbb Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 6 Apr 2016 13:10:46 -0700 Subject: gpu: nvgpu: gp10b: Add litter values HAL Move per-chip constants to be returned by a chip specific function. Implement get_litter_value() for each chip. Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1121384 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 74 +++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 427936c7..ea5e3f15 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -42,6 +42,7 @@ #include #include "gp10b.h" +#include "hw_proj_gp10b.h" #define FUSE_OPT_PRIV_SEC_EN_0 0x264 #define PRIV_SECURITY_ENABLED 0x01 @@ -99,6 +100,78 @@ static struct gpu_ops gp10b_ops = { } }; +static int gp10b_get_litter_value(struct gk20a *g, + enum nvgpu_litter_value value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + default: + break; + } + + return ret; +} + int gp10b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; @@ -156,6 +229,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_therm_ops(gops); gops->name = "gp10b"; gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; + gops->get_litter_value = gp10b_get_litter_value; c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; -- cgit v1.2.2 From 1e67de6e6ea930091bee381ff4a96ae0ca0c76d6 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 9 May 2016 15:27:36 -0700 Subject: gpu: nvgpu: init tsg HAL ops Bug 1702773 Change-Id: I9b6e1d0f2f4fe979f6fab83347884bd69413ccda Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1144935 (cherry picked from commit f79eb75272879c869b137cd042312db0a5953412) Reviewed-on: http://git-master/r/1127031 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index ea5e3f15..a75d2604 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -227,6 +227,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_regops(gops); gp10b_init_cde_ops(gops); gp10b_init_therm_ops(gops); + gk20a_init_tsg_ops(gops); gops->name = "gp10b"; gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; gops->get_litter_value = gp10b_get_litter_value; -- cgit v1.2.2 From 9454529abe0ac42d15df01e36898cd2c840de9c8 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:39:52 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a75d2604..b8fffab3 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -25,7 +25,7 @@ #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" -#include "gp10b/ce2_gp10b.h" +#include "gp10b/ce_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" @@ -150,6 +150,9 @@ static int gp10b_get_litter_value(struct gk20a *g, case GPU_LIT_ROP_SHARED_BASE: ret = proj_rop_shared_base_v(); break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; case GPU_LIT_HOST_NUM_PBDMA: ret = proj_host_num_pbdma_v(); break; @@ -219,7 +222,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_ltc(gops); gp10b_init_fb(gops); gp10b_init_fifo(gops); - gp10b_init_ce2(gops); + gp10b_init_ce(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); -- cgit v1.2.2 From 14e0681fe5bb39b1773c06c51bc56101a9a1ca40 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 3 Jun 2016 15:55:35 -0700 Subject: gpu: nvgpu: set gops.read_ptimer Bug 1395833 Change-Id: I7e7f453d83db76a46f79d62f205832254fcf401e Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1159589 (cherry picked from commit a1f43172ebf91066969c4d9e25b8a781edb20724) Reviewed-on: http://git-master/r/1158898 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b8fffab3..e44767a0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -234,6 +234,7 @@ int gp10b_init_hal(struct gk20a *g) gops->name = "gp10b"; gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; gops->get_litter_value = gp10b_get_litter_value; + gops->read_ptimer = gk20a_read_ptimer; c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; -- cgit v1.2.2 From f61d819accfd90a8db59799f36f9ec97e97424f0 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 3 Jun 2016 15:29:57 -0700 Subject: gpu: nvgpu: ppc register support Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: I1d04bfd20eac08a26986a2436524b97a008ed913 Signed-off-by: Peter Daifuku Reviewed-on: http://git-master/r/1158889 (cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433) Reviewed-on: http://git-master/r/1164398 (cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a) Reviewed-on: http://git-master/r/1181501 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e44767a0..d82a03eb 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -138,9 +138,15 @@ static int gp10b_get_litter_value(struct gk20a *g, case GPU_LIT_TPC_IN_GPC_SHARED_BASE: ret = proj_tpc_in_gpc_shared_base_v(); break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; + case GPU_LIT_PPC_IN_GPC_SHARED_BASE: + ret = proj_ppc_in_gpc_shared_base_v(); + break; case GPU_LIT_ROP_BASE: ret = proj_rop_base_v(); break; @@ -169,6 +175,8 @@ static int gp10b_get_litter_value(struct gk20a *g, ret = proj_fbpa_stride_v(); break; default: + gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); + BUG(); break; } -- cgit v1.2.2 From a5fad1ec42d3f1ef1391bed8c768e0b3aa0f3fab Mon Sep 17 00:00:00 2001 From: Hoang Pham Date: Fri, 22 Jul 2016 09:59:32 -0700 Subject: Revert "gpu: nvgpu: ppc register support" This reverts commit 3639659575e76f81e31c5c9f3aca8896c4ebcb69. Change-Id: Ieb6a40e30128bb9c59f64f6e39bb026de9a30397 Signed-off-by: Hoang Pham Reviewed-on: http://git-master/r/1189599 Reviewed-by: Vladislav Buzov Tested-by: Vladislav Buzov --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d82a03eb..e44767a0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -138,15 +138,9 @@ static int gp10b_get_litter_value(struct gk20a *g, case GPU_LIT_TPC_IN_GPC_SHARED_BASE: ret = proj_tpc_in_gpc_shared_base_v(); break; - case GPU_LIT_PPC_IN_GPC_BASE: - ret = proj_ppc_in_gpc_base_v(); - break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; - case GPU_LIT_PPC_IN_GPC_SHARED_BASE: - ret = proj_ppc_in_gpc_shared_base_v(); - break; case GPU_LIT_ROP_BASE: ret = proj_rop_base_v(); break; @@ -175,8 +169,6 @@ static int gp10b_get_litter_value(struct gk20a *g, ret = proj_fbpa_stride_v(); break; default: - gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); - BUG(); break; } -- cgit v1.2.2 From cb80b2315db303e7f27dbbc5a37d1e9eb72ae8e6 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 3 Jun 2016 15:29:57 -0700 Subject: gpu: nvgpu: ppc register support Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: Icb0bdedbe78ec4246426789e62302118682ed20a Signed-off-by: Peter Daifuku Reviewed-on: http://git-master/r/1158889 (cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433) Reviewed-on: http://git-master/r/1164398 (cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a) Reviewed-on: http://git-master/r/1181501 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1189608 Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e44767a0..d82a03eb 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -138,9 +138,15 @@ static int gp10b_get_litter_value(struct gk20a *g, case GPU_LIT_TPC_IN_GPC_SHARED_BASE: ret = proj_tpc_in_gpc_shared_base_v(); break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; + case GPU_LIT_PPC_IN_GPC_SHARED_BASE: + ret = proj_ppc_in_gpc_shared_base_v(); + break; case GPU_LIT_ROP_BASE: ret = proj_rop_base_v(); break; @@ -169,6 +175,8 @@ static int gp10b_get_litter_value(struct gk20a *g, ret = proj_fbpa_stride_v(); break; default: + gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); + BUG(); break; } -- cgit v1.2.2 From 436109f46d49a24b69bab7c85b112f192ab002c0 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 7 Jul 2016 15:01:00 -0700 Subject: gpu: nvgpu: gp10b: add is_fmodel check Check for is_fmodel instead of check for simualtion platforms. Bug 1735760 Change-Id: I14e349088e9414a73353a94613fa031e63bfa31f Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1177200 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Tejal Kudav Reviewed-by: Ayoosh Bansal Reviewed-by: Adeel Raza --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d82a03eb..87ba5bf6 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -187,11 +187,12 @@ int gp10b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + struct gk20a_platform *platform = dev_get_drvdata(g->dev); *gops = gp10b_ops; #ifdef CONFIG_TEGRA_ACR - if (tegra_platform_is_linsim()) { + if (platform->is_fmodel) { gops->privsecurity = 0; gops->securegpccs = 0; } else { @@ -206,8 +207,8 @@ int gp10b_init_hal(struct gk20a *g) } } #else - if (tegra_platform_is_linsim()) { - gk20a_dbg_info("running ASIM with PRIV security disabled"); + if (platform->is_fmodel) { + gk20a_dbg_info("running simulator with PRIV security disabled"); gops->privsecurity = 0; gops->securegpccs = 0; } else { -- cgit v1.2.2 From 0e1758a723541ad9b4507bc34737f4f0f25e2418 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 17 Jun 2016 15:26:24 -0700 Subject: gpu: nvgpu: move dbg_session_ops to gops Move dbg_session_ops to gops for better code consistency JIRA VFND-1905 Change-Id: I0ac10a69194c8ca485f361cd8cea61d8ab72145a Signed-off-by: Peter Daifuku Reviewed-on: http://git-master/r/1192642 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 87ba5bf6..ae92608c 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -43,6 +43,7 @@ #include "gp10b.h" #include "hw_proj_gp10b.h" +#include "gk20a/dbg_gpu_gk20a.h" #define FUSE_OPT_PRIV_SEC_EN_0 0x264 #define PRIV_SECURITY_ENABLED 0x01 @@ -236,6 +237,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); + gk20a_init_dbg_session_ops(gops); gp10b_init_regops(gops); gp10b_init_cde_ops(gops); gp10b_init_therm_ops(gops); -- cgit v1.2.2 From a74a971f498084bf9131be3964c380c74e9d5960 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Wed, 7 Sep 2016 17:27:45 -0700 Subject: gpu: nvgpu: vgpu: cyclestat snapshot support Add support for cyclestats snapshots in the virtual case Bug 1700143 JIRA EVLR-278 Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b Signed-off-by: Peter Daifuku Reviewed-on: http://git-master/r/1216644 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index ae92608c..ec81cf35 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -44,6 +44,7 @@ #include "gp10b.h" #include "hw_proj_gp10b.h" #include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/css_gr_gk20a.h" #define FUSE_OPT_PRIV_SEC_EN_0 0x264 #define PRIV_SECURITY_ENABLED 0x01 @@ -242,6 +243,9 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_cde_ops(gops); gp10b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); +#if defined(CONFIG_GK20A_CYCLE_STATS) + gk20a_init_css_ops(gops); +#endif gops->name = "gp10b"; gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; gops->get_litter_value = gp10b_get_litter_value; -- cgit v1.2.2 From 49840c15efb36b3216357b93ba0477e53dbef3b6 Mon Sep 17 00:00:00 2001 From: Shardar Shariff Md Date: Fri, 9 Sep 2016 02:36:04 +0530 Subject: gpu: nvgpu: change the usage of tegra_fuse_readl tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086 Signed-off-by: Shardar Shariff Md Reviewed-on: http://git-master/r/1217376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index ec81cf35..c4e44483 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -190,6 +190,7 @@ int gp10b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; struct gk20a_platform *platform = dev_get_drvdata(g->dev); + u32 val; *gops = gp10b_ops; @@ -198,8 +199,8 @@ int gp10b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; } else { - if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & - PRIV_SECURITY_ENABLED) { + tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val); + if (val & PRIV_SECURITY_ENABLED) { gops->privsecurity = 1; gops->securegpccs =1; } else { @@ -214,8 +215,8 @@ int gp10b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; } else { - if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & - PRIV_SECURITY_ENABLED) { + tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val); + if (val & PRIV_SECURITY_ENABLED) { gk20a_dbg_info("priv security is not supported but enabled"); gops->privsecurity = 1; gops->securegpccs =1; -- cgit v1.2.2 From 432017248e432df0619dc2df30f915a52634338f Mon Sep 17 00:00:00 2001 From: Vijayakumar Subbu Date: Sat, 30 Jul 2016 10:44:30 -0700 Subject: gpu: nvgpu: Add dGPU clocks support JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index c4e44483..2699dd7a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -193,7 +193,7 @@ int gp10b_init_hal(struct gk20a *g) u32 val; *gops = gp10b_ops; - + gops->pmupstate = false; #ifdef CONFIG_TEGRA_ACR if (platform->is_fmodel) { gops->privsecurity = 0; -- cgit v1.2.2 From 3a032c33fb70453494e0b143a93db61f859381ea Mon Sep 17 00:00:00 2001 From: Shardar Shariff Md Date: Tue, 1 Nov 2016 19:09:46 +0530 Subject: gpu: nvgpu: gp10b: define fuse macro depend on kernel version - Define fuse macros depending on kernel version as fuse offset got changed in K4.4 and for K4.4 fuse defines are defined in common header file (tegra-fuse.h) - Use fuse control read/write APIs when reading control registers for K4.4 Bug 200243956 Change-Id: I34dabd1a307d10010cb89ac6a5f1e3f5b177c0fc Signed-off-by: Shardar Shariff Md Reviewed-on: http://git-master/r/1245825 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2699dd7a..f0137a70 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -15,6 +15,7 @@ #include #include +#include #include @@ -46,7 +47,9 @@ #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/css_gr_gk20a.h" +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) #define FUSE_OPT_PRIV_SEC_EN_0 0x264 +#endif #define PRIV_SECURITY_ENABLED 0x01 static struct gpu_ops gp10b_ops = { -- cgit v1.2.2 From 90fbd43cbeb1439dd633f28f9a28b0f4e1cba1a3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 11 Nov 2016 17:03:25 -0800 Subject: gpu: nvgpu: gp10x: updated API for get_litter_value get_litter_value API is updated to use int instead of enum type. JIRA GV11B-21 Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1252212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index f0137a70..e9385db0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -105,8 +105,7 @@ static struct gpu_ops gp10b_ops = { } }; -static int gp10b_get_litter_value(struct gk20a *g, - enum nvgpu_litter_value value) +static int gp10b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { -- cgit v1.2.2 From 06a03fba267ce34c3a601941f25476ae937da1fc Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Thu, 3 Nov 2016 16:14:05 -0700 Subject: gpu: nvgpu: add FBPA base addresses Add FBPA base addresses Bug 200249125 Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b Signed-off-by: Peter Daifuku Reviewed-on: http://git-master/r/1247802 (cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a) Reviewed-on: http://git-master/r/1252163 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e9385db0..b92bdfe2 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -178,6 +178,12 @@ static int gp10b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; + case GPU_LIT_FBPA_BASE: + ret = proj_fbpa_base_v(); + break; + case GPU_LIT_FBPA_SHARED_BASE: + ret = proj_fbpa_shared_base_v(); + break; default: gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); BUG(); -- cgit v1.2.2 From d8dc7b130e4b93a1c29c26b852af686eb67444de Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Thu, 17 Nov 2016 16:38:57 -0800 Subject: gpu: nvgpu: hardcode gp10b fbpa values gp10b does not have an fbpa unit, although the hw header files claim it does. Hardcode all fbpa values to 0. Bug 200249125 Change-Id: I6ed63b3231d7af8e31ccf5047d56bdb85f05a9d9 Signed-off-by: Peter Daifuku Reviewed-on: http://git-master/r/1256422 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b92bdfe2..a656f10d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -172,17 +172,15 @@ static int gp10b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_LTS_STRIDE: ret = proj_lts_stride_v(); break; + /* GP10B does not have a FBPA unit, despite what's listed in the + * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS, + * so hardcode all values to 0. + */ case GPU_LIT_NUM_FBPAS: - ret = proj_scal_litter_num_fbpas_v(); - break; case GPU_LIT_FBPA_STRIDE: - ret = proj_fbpa_stride_v(); - break; case GPU_LIT_FBPA_BASE: - ret = proj_fbpa_base_v(); - break; case GPU_LIT_FBPA_SHARED_BASE: - ret = proj_fbpa_shared_base_v(); + ret = 0; break; default: gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); -- cgit v1.2.2