From ce85eae72a1aa54518fae68ef616e9b95bccb052 Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Tue, 3 Mar 2015 17:29:19 +0200 Subject: gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointer Fixed incorrectly encoded pointer and size. bug 1525327 bug 1581799 Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b Signed-off-by: Kirill Artamonov Reviewed-on: http://git-master/r/713209 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 271a6d0c..4d0de15f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -664,8 +664,9 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << + (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); + size = gr_ctx->t18x.spill_ctxsw_buffer.size; gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_swdx_rm_spill_buffer_addr_r(), @@ -673,7 +674,7 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, true); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_swdx_rm_spill_buffer_size_r(), - gr_gpc0_swdx_rm_spill_buffer_size_256b_f(addr), + gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), true); cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); -- cgit v1.2.2