From c320ccfa952a2796db27d97111791bcbeff9f5c7 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Dec 2016 11:46:17 +0530 Subject: gpu: nvgpu: remove debugger check for cilp completion event We can trigger CILP only if SM debug mode is on. So in fecs interrupt handler, we could have graphics context running for which SM debug mode is disabled. And in that case we skip posting of cilp completion events to UMD. But since CILP event was anyways triggered, we need to post events to UMD irrespective of SM debug mode is enabled at that point or not Hence remove check gk20a_gr_sm_debugger_attached() for posting events to UMD Bug 200243092 Change-Id: I54ad205be11ec6d5034d524bfbb28f8a1fa72993 Signed-off-by: Deepak Nibade Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1263591 (cherry picked from commit e6259e2d0d5a4bb5929e70e03e154f8b82ae3600) Reviewed-on: http://git-master/r/1264780 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 09c2558c..051e16a3 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1896,18 +1896,17 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g, goto clean_up; } - if (gk20a_gr_sm_debugger_attached(g)) { - gk20a_dbg_gpu_post_events(ch); + /* Post events to UMD */ + gk20a_dbg_gpu_post_events(ch); - if (gk20a_is_channel_marked_as_tsg(ch)) { - struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; + if (gk20a_is_channel_marked_as_tsg(ch)) { + struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; - gk20a_tsg_event_id_post_event(tsg, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); - } else { - gk20a_channel_event_id_post_event(ch, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); - } + gk20a_tsg_event_id_post_event(tsg, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); + } else { + gk20a_channel_event_id_post_event(ch, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); } gk20a_channel_put(ch); -- cgit v1.2.2