From 29b688960fcf6279f58d95f7e17f31ef15129a80 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 15:39:27 -0700 Subject: gpu: nvgpu: add suspend_all_sms gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512215 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 5d17472f..afd3750b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1822,7 +1822,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", gpc, tpc); - gk20a_suspend_all_sms(g, global_mask, false); + g->ops.gr.suspend_all_sms(g, global_mask, false); gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); } else { @@ -1991,7 +1991,7 @@ static bool gr_gp10b_suspend_context(struct channel_gk20a *ch, *cilp_preempt_pending = false; if (gk20a_is_channel_ctx_resident(ch)) { - gk20a_suspend_all_sms(g, 0, false); + g->ops.gr.suspend_all_sms(g, 0, false); if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { err = gr_gp10b_set_cilp_preempt_pending(g, ch); -- cgit v1.2.2