From 1fcd7fd547daac5374993f243fad77a822a5a048 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Wed, 1 Apr 2015 18:15:44 +0300 Subject: gpu: nvgpu: set zbc format field properly Add a missing bitmask for clearing existing bits before setting a new value, and shift the value the correct amount. Also format register needs to be rounded down. Bug 200087330 Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c Signed-off-by: Konsta Holtta Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/726265 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a2c981a0..4f7a037b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -203,9 +203,10 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]); gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]); gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); - zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4)); - zbc_c |= color_val->format << (index % 4) * 6; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); + zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); + zbc_c &= ~(0x7f << ((index % 4) * 7)); + zbc_c |= color_val->format << ((index % 4) * 7); + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); return 0; } @@ -240,9 +241,10 @@ static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, gr->zbc_dep_tbl[index].ref_cnt++; gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); - zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4)); - zbc_z |= depth_val->format << (index % 4) * 6; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); + zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); + zbc_z &= ~(0x7f << (index % 4) * 7); + zbc_z |= depth_val->format << (index % 4) * 7; + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); return 0; } -- cgit v1.2.2