From 1ab0eec6eae303fa2b2f7cc97b78aed4a9f895e5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 16:43:31 -0700 Subject: gpu: nvgpu: add resume_single_sm gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index afd3750b..a1be22df 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1860,7 +1860,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: resume for gpc %d tpc %d\n", gpc, tpc); - gk20a_resume_single_sm(g, gpc, tpc); + g->ops.gr.resume_single_sm(g, gpc, tpc, sm); *ignore_debugger = true; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); -- cgit v1.2.2