From 0e2e3898f7f8828ff9601d414f730b9fa8d09b3f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 15:33:42 -0700 Subject: gpu: nvgpu: add suspend_single_sm gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512214 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 2a3ecd31..5d17472f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1829,7 +1829,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: STOP_TRIGGER from gpc %d tpc %d\n", gpc, tpc); - gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); + g->ops.gr.suspend_single_sm(g, gpc, tpc, sm, global_mask, true); } /* reset the HWW errors after locking down */ -- cgit v1.2.2