From dd739fcb039d51606e9a5454ec0aab17bcb01965 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 18 Apr 2018 19:39:46 -0700 Subject: gpu: nvgpu: Remove gk20a_dbg* functions Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 86a2b751..e2ad1bd3 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c @@ -1,7 +1,7 @@ /* * Pascal GPU series Copy Engine. * - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,14 +30,14 @@ static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) { - gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); + nvgpu_log(g, gpu_dbg_intr, "ce blocking pipe interrupt\n"); return ce_intr_status_blockpipe_pending_f(); } static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr) { - gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); + nvgpu_log(g, gpu_dbg_intr, "ce launch error interrupt\n"); return ce_intr_status_launcherr_pending_f(); } @@ -47,7 +47,7 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); u32 clear_intr = 0; - gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); + nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); /* clear blocking interrupts: they exibit broken behavior */ if (ce_intr & ce_intr_status_blockpipe_pending_f()) @@ -65,7 +65,7 @@ int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) int ops = 0; u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); - gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); + nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { gk20a_writel(g, ce_intr_status_r(inst_id), -- cgit v1.2.2