From 5c9bedf6f6e3213cd830d045d70f61de49f6e42b Mon Sep 17 00:00:00 2001 From: Srirangan Date: Thu, 23 Aug 2018 12:57:45 +0530 Subject: gpu: nvgpu: gp10b: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Ib5961506b0f95867a57f8c0d7024568785fe7b93 Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1797332 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 76179b78..0c07c069 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c @@ -51,11 +51,13 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); /* clear blocking interrupts: they exibit broken behavior */ - if (ce_intr & ce_intr_status_blockpipe_pending_f()) + if (ce_intr & ce_intr_status_blockpipe_pending_f()) { clear_intr |= ce_blockpipe_isr(g, ce_intr); + } - if (ce_intr & ce_intr_status_launcherr_pending_f()) + if (ce_intr & ce_intr_status_launcherr_pending_f()) { clear_intr |= ce_launcherr_isr(g, ce_intr); + } gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); return; -- cgit v1.2.2