From 403874fa75dbb00e974a8d0f88b6e92be01ba42e Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 6 Feb 2017 15:44:55 -0800 Subject: gpu: nvgpu: refactor interrupt handling JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1312796 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M Reviewed-by: Terje Bergstrom Reviewed-by: Navneet Kumar --- drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index f19a4b0f..169309fa 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c @@ -1,7 +1,7 @@ /* * Pascal GPU series Copy Engine. * - * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,15 +22,6 @@ #include -static void ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); - - /* wake theads waiting in this channel */ - gk20a_channel_semaphore_wakeup(g, true); - return; -} - static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) { gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); @@ -63,8 +54,9 @@ static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) return; } -static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +static int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { + int ops = 0; u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); @@ -72,10 +64,11 @@ static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { gk20a_writel(g, ce_intr_status_r(inst_id), ce_intr_status_nonblockpipe_pending_f()); - ce_nonblockpipe_isr(g, ce_intr); + ops |= (gk20a_nonstall_ops_wakeup_semaphore | + gk20a_nonstall_ops_post_events); } - return; + return ops; } void gp10b_init_ce(struct gpu_ops *gops) { -- cgit v1.2.2