From 9454529abe0ac42d15df01e36898cd2c840de9c8 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:39:52 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 83 ------------------------------------- 1 file changed, 83 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.c (limited to 'drivers/gpu/nvgpu/gp10b/ce2_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c deleted file mode 100644 index 4cb13f3b..00000000 --- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * GK20A Graphics Copy Engine (gr host) - * - * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ -#include "hw_ce2_gp10b.h" -#include "ce2_gp10b.h" - -static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); - - /* wake theads waiting in this channel */ - gk20a_channel_semaphore_wakeup(g, true); - return ce2_intr_status_nonblockpipe_pending_f(); -} - -static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); - - return ce2_intr_status_blockpipe_pending_f(); -} - -static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); - - return ce2_intr_status_launcherr_pending_f(); -} - -static void gp10b_ce2_isr(struct gk20a *g) -{ - u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); - u32 clear_intr = 0; - - gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); - - /* clear blocking interrupts: they exibit broken behavior */ - if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) - clear_intr |= ce2_blockpipe_isr(g, ce2_intr); - - if (ce2_intr & ce2_intr_status_launcherr_pending_f()) - clear_intr |= ce2_launcherr_isr(g, ce2_intr); - - gk20a_writel(g, ce2_intr_status_r(0), clear_intr); - return; -} - -static void gp10b_ce2_nonstall_isr(struct gk20a *g) -{ - u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); - u32 clear_intr = 0; - - gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); - - if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) - clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); - - gk20a_writel(g, ce2_intr_status_r(0), clear_intr); - - return; -} -void gp10b_init_ce2(struct gpu_ops *gops) -{ - gops->ce2.isr_stall = gp10b_ce2_isr; - gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr; -} -- cgit v1.2.2