From 80bf7419179223e6893e3549fd0a192804149eda Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Jun 2018 14:39:59 +0530 Subject: gpu: nvgpu: gp106 SEC2 falcon code update - Added prefix gp106_ to sec2_wait_for_halt() & sec2_clear_halt_interrupt_status() for gp106 SEC2 HAL - Made changes to gp106_sec2_wait_for_halt() to read SEC2 falcon mailbox using common falcon mailbox access functions. - Add define for falcon mailbox - These changes are done to reuse gp106 HAL's for GPU_NEXT. Change-Id: Id32a7636d775b482684212ed4ef5d01c8ea65335 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1755618 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 ++-- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 10 ++++++---- drivers/gpu/nvgpu/gp106/sec2_gp106.h | 5 +++-- 3 files changed, 11 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106') diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index a22350ce..9427d3bf 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -621,9 +621,9 @@ static const struct gpu_ops gp106_ops = { .alloc_blob_space = gp106_alloc_blob_space, .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, - .falcon_wait_for_halt = sec2_wait_for_halt, + .falcon_wait_for_halt = gp106_sec2_wait_for_halt, .falcon_clear_halt_interrupt_status = - sec2_clear_halt_interrupt_status, + gp106_sec2_clear_halt_interrupt_status, .init_falcon_setup_hw = init_sec2_setup_hw1, .pmu_queue_tail = gk20a_pmu_queue_tail, .pmu_get_queue_head = pwr_pmu_queue_head_r, diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 1c959022..d480d875 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -34,7 +34,8 @@ #define gm20b_dbg_pmu(g, fmt, arg...) \ nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) -int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) +int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, + unsigned int timeout) { int status = 0; @@ -44,7 +45,7 @@ int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) return status; } -int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) +int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) { u32 data = 0; int completion = 0; @@ -55,9 +56,10 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) goto exit; } - g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r()); + g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, + FALCON_MAILBOX_1); gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); - data = gk20a_readl(g, psec_falcon_mailbox0_r()); + data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); if (data) { nvgpu_err(g, "ACR boot failed, err %x", data); completion = -EAGAIN; diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h index 1fe94bb8..cab3ca5d 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h @@ -23,8 +23,9 @@ #ifndef __SEC2_H_ #define __SEC2_H_ -int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); -int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); +int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, + unsigned int timeout); +int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, void *desc, u32 bl_sz); void init_pmu_setup_hw1(struct gk20a *g); -- cgit v1.2.2