From 673dd971600b26131c0afdb221e13c080da022fd Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 10 May 2017 20:35:24 +0530 Subject: gpu: nvgpu: moved & renamed "struct pmu_gk20a" - Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/acr_gp106.c | 13 +++++++------ drivers/gpu/nvgpu/gp106/pmu_gp106.c | 14 ++++++++------ drivers/gpu/nvgpu/gp106/sec2_gp106.c | 12 +++++++----- drivers/gpu/nvgpu/gp106/sec2_gp106.h | 10 +++++----- 4 files changed, 27 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106') diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 5570489e..c7d71ab0 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -140,7 +141,7 @@ void gp106_init_secure_pmu(struct gpu_ops *gops) static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) { struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig; - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct lsf_ucode_desc_v1 *lsf_desc; int err; @@ -382,7 +383,7 @@ static int gp106_prepare_ucode_blob(struct gk20a *g) int err; struct ls_flcn_mgr_v1 lsfm_l, *plsfm; - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct wpr_carveout_info wpr_inf; if (g->acr.ucode_blob.cpu_va) { @@ -445,7 +446,7 @@ static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, static int lsfm_discover_ucode_images(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct flcn_ucode_img_v1 ucode_img; u32 falcon_id; u32 i; @@ -531,7 +532,7 @@ static int gp106_pmu_populate_loader_cfg(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size) { struct wpr_carveout_info wpr_inf; - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct lsfm_managed_ucode_img_v2 *p_lsfm = (struct lsfm_managed_ucode_img_v2 *)lsfm; struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img); @@ -661,7 +662,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, struct lsfm_managed_ucode_img_v2 *pnode) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; if (pnode->wpr_header.falcon_id != pmu->falcon_id) { gp106_dbg_pmu("non pmu. write flcn bl gen desc\n"); g->ops.pmu.flcn_populate_bl_dmem_desc(g, @@ -818,7 +819,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; u32 full_app_size = 0; u32 data = 0; diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 467c50be..89144c2a 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c @@ -11,6 +11,8 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -31,7 +33,7 @@ #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 -static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) +static int gp106_pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable) { struct gk20a *g = gk20a_from_pmu(pmu); @@ -86,7 +88,7 @@ static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) } } -static int pmu_enable(struct pmu_gk20a *pmu, bool enable) +static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) { struct gk20a *g = gk20a_from_pmu(pmu); u32 reg_reset; @@ -121,7 +123,7 @@ static int pmu_enable(struct pmu_gk20a *pmu, bool enable) int gp106_pmu_reset(struct gk20a *g) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; int err = 0; gk20a_dbg_fn(""); @@ -210,7 +212,7 @@ static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg, static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; u32 seq; u32 status; @@ -262,7 +264,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct pmu_pg_stats_v2 stats; pmu_copy_from_dmem(pmu, @@ -335,7 +337,7 @@ static bool gp106_is_priv_load(u32 falcon_id) static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, u32 flags) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; u32 seq; diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 078a1436..9c86c5b5 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -11,6 +11,8 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -88,7 +90,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) return completion; } -void sec2_copy_to_dmem(struct pmu_gk20a *pmu, +void sec2_copy_to_dmem(struct nvgpu_pmu *pmu, u32 dst, u8 *src, u32 size, u8 port) { struct gk20a *g = gk20a_from_pmu(pmu); @@ -139,7 +141,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu, return; } -int bl_bootstrap_sec2(struct pmu_gk20a *pmu, +int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, void *desc, u32 bl_sz) { struct gk20a *g = gk20a_from_pmu(pmu); @@ -223,7 +225,7 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu, return 0; } -void sec_enable_irq(struct pmu_gk20a *pmu, bool enable) +void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable) { struct gk20a *g = gk20a_from_pmu(pmu); @@ -281,7 +283,7 @@ void sec_enable_irq(struct pmu_gk20a *pmu, bool enable) void init_pmu_setup_hw1(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; /* PMU TRANSCFG */ /* setup apertures - virtual */ @@ -331,7 +333,7 @@ void init_pmu_setup_hw1(struct gk20a *g) int init_sec2_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz) { - struct pmu_gk20a *pmu = &g->pmu; + struct nvgpu_pmu *pmu = &g->pmu; int err; u32 data = 0; diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h index 336bb0f0..e3da0abf 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,12 +16,12 @@ int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); -void sec2_copy_to_dmem(struct pmu_gk20a *pmu, +void sec2_copy_to_dmem(struct nvgpu_pmu *pmu, u32 dst, u8 *src, u32 size, u8 port); -void sec2_dump_falcon_stats(struct pmu_gk20a *pmu); -int bl_bootstrap_sec2(struct pmu_gk20a *pmu, +void sec2_dump_falcon_stats(struct nvgpu_pmu *pmu); +int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, void *desc, u32 bl_sz); -void sec_enable_irq(struct pmu_gk20a *pmu, bool enable); +void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable); void init_pmu_setup_hw1(struct gk20a *g); int init_sec2_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); -- cgit v1.2.2