From 66ec347db401affd8bcd425dc123e7162b9ae3bb Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 30 Jun 2017 15:53:08 -0700 Subject: gpu: nvgpu: Reorg fifo HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp106/fifo_gp106.c | 11 ++---- drivers/gpu/nvgpu/gp106/fifo_gp106.h | 6 ++-- drivers/gpu/nvgpu/gp106/hal_gp106.c | 68 ++++++++++++++++++++++++++++++++++-- 3 files changed, 71 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106') diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.c b/drivers/gpu/nvgpu/gp106/fifo_gp106.c index 5fa03d6f..22a49260 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.c +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,14 +19,7 @@ #include #include -static u32 gp106_fifo_get_num_fifos(struct gk20a *g) +u32 gp106_fifo_get_num_fifos(struct gk20a *g) { return ccsr_channel__size_1_v(); } - -void gp106_init_fifo(struct gpu_ops *gops) -{ - gp10b_init_fifo(gops); - gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos; - gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; -} diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.h b/drivers/gpu/nvgpu/gp106/fifo_gp106.h index 1bcec9ef..c70c0995 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.h +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -13,6 +13,6 @@ #ifndef NVGPU_FIFO_GP106_H #define NVGPU_FIFO_GP106_H -struct gpu_ops; -void gp106_init_fifo(struct gpu_ops *gops); +struct gk20a; +u32 gp106_fifo_get_num_fifos(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 1690c42b..fa767c3b 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -14,6 +14,7 @@ */ #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -31,6 +32,7 @@ #include "gp10b/regops_gp10b.h" #include "gp10b/cde_gp10b.h" #include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" #include "gp106/fifo_gp106.h" #include "gp106/regops_gp106.h" @@ -62,6 +64,9 @@ #include #include +#include +#include +#include static int gp106_get_litter_value(struct gk20a *g, int value) { @@ -243,6 +248,66 @@ static const struct gpu_ops gp106_ops = { .pg_gr_load_gating_prod = gr_gp106_pg_gr_load_gating_prod, }, + .fifo = { + .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = gk20a_fifo_channel_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gp10b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gk20a_fifo_userd_gp_get, + .userd_gp_put = gk20a_fifo_userd_gp_put, + .userd_pb_get = gk20a_fifo_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gk20a_fifo_preempt_channel, + .preempt_tsg = gk20a_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, + .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gp106_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, + .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gk20a_dump_eng_status, + .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, + .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, + .is_preempt_pending = gk20a_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, + .handle_sched_error = gk20a_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = gp10b_fifo_resetup_ramfc, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + }, .mc = { .intr_enable = mc_gp10b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -331,6 +396,7 @@ int gp106_init_hal(struct gk20a *g) gops->ltc = gp106_ops.ltc; gops->clock_gating = gp106_ops.clock_gating; + gops->fifo = gp106_ops.fifo; gops->mc = gp106_ops.mc; gops->debug = gp106_ops.debug; gops->dbg_session_ops = gp106_ops.dbg_session_ops; @@ -358,7 +424,6 @@ int gp106_init_hal(struct gk20a *g) gp106_init_gr(gops); gp10b_init_fecs_trace_ops(gops); gp106_init_fb(gops); - gp106_init_fifo(gops); gp10b_init_ce(gops); gp106_init_gr_ctx(gops); gp106_init_mm(gops); @@ -366,7 +431,6 @@ int gp106_init_hal(struct gk20a *g) gp106_init_clk_ops(gops); gp106_init_clk_arb_ops(gops); gp106_init_regops(gops); - gk20a_init_tsg_ops(gops); gk20a_init_pramin_ops(gops); gp106_init_therm_ops(gops); -- cgit v1.2.2