From 4efdc362175c67f93d3546727c8825686619c1cb Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 19 Sep 2018 12:23:05 +0530 Subject: gpu: nvgpu: ACR load split feature support -Added code to copy SEC2-RTOS ucode to non-wpr blob as part of prepare ucode blob. -Added code to setup & bootstrap GSP, as ACR-ASB needs ucode to execute on GSP falcon. -Defined LSF_FALCON_ID_GSPLITE for GSP falcon -Defined HSBIN_ACR_AHESASC_DBG/PROD_UCODE & HSBIN_ACR_ASB_DBG/PROD_UCODE to hold names of ACR AHESASC/ASB ucodes. -Added defines to hold name of SE2C RTOS ucodes JIRA NVGPUT-134 Change-Id: I824afed41f785a4ca0fb393bd023db5396c7a399 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1790179 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/acr_gp106.c | 68 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp106/acr_gp106.h | 1 + 2 files changed, 69 insertions(+) (limited to 'drivers/gpu/nvgpu/gp106') diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 2a4ee6d5..f5ae565a 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c @@ -67,6 +67,7 @@ static get_ucode_details pmu_acr_supp_ucode_list[] = { pmu_ucode_details, fecs_ucode_details, gpccs_ucode_details, + sec2_ucode_details, }; void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) @@ -388,6 +389,73 @@ rel_sig: return err; } +int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) +{ + struct nvgpu_firmware *sec2_fw, *sec2_desc, *sec2_sig; + struct pmu_ucode_desc_v1 *desc; + struct lsf_ucode_desc_v1 *lsf_desc; + u32 *ucode_image; + int err = 0; + + gp106_dbg_pmu(g, "requesting SEC2 ucode in %s", g->name); + sec2_fw = nvgpu_request_firmware(g, LSF_SEC2_UCODE_IMAGE_BIN, + NVGPU_REQUEST_FIRMWARE_NO_SOC); + if (sec2_fw == NULL) { + nvgpu_err(g, "failed to load sec2 ucode!!"); + return -ENOENT; + } + + ucode_image = (u32 *)sec2_fw->data; + + gp106_dbg_pmu(g, "requesting SEC2 ucode desc in %s", g->name); + sec2_desc = nvgpu_request_firmware(g, LSF_SEC2_UCODE_DESC_BIN, + NVGPU_REQUEST_FIRMWARE_NO_SOC); + if (sec2_desc == NULL) { + nvgpu_err(g, "failed to load SEC2 ucode desc!!"); + err = -ENOENT; + goto release_img_fw; + } + + desc = (struct pmu_ucode_desc_v1 *)sec2_desc->data; + + sec2_sig = nvgpu_request_firmware(g, LSF_SEC2_UCODE_SIG_BIN, + NVGPU_REQUEST_FIRMWARE_NO_SOC); + if (sec2_sig == NULL) { + nvgpu_err(g, "failed to load SEC2 sig!!"); + err = -ENOENT; + goto release_desc; + } + + lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1)); + if (lsf_desc == NULL) { + err = -ENOMEM; + goto release_sig; + } + + memcpy(lsf_desc, (void *)sec2_sig->data, + min_t(size_t, sizeof(*lsf_desc), sec2_sig->size)); + + lsf_desc->falcon_id = LSF_FALCON_ID_SEC2; + + p_img->desc = desc; + p_img->data = ucode_image; + p_img->data_size = desc->app_start_offset + desc->app_size; + p_img->fw_ver = NULL; + p_img->header = NULL; + p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; + + gp106_dbg_pmu(g, "requesting SEC2 ucode in %s done", g->name); + + return err; +release_sig: + nvgpu_release_firmware(g, sec2_sig); +release_desc: + nvgpu_release_firmware(g, sec2_desc); +release_img_fw: + nvgpu_release_firmware(g, sec2_fw); + return err; +} + /* * Discover all supported shared data falcon SUB WPRs */ diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h index ad004bf0..0fe3d119 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h @@ -53,6 +53,7 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img); int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img); +int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img); int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id); int lsfm_discover_ucode_images(struct gk20a *g, -- cgit v1.2.2