From 0e58ebaae13dd59b6aba5297f898e7c89fcd2742 Mon Sep 17 00:00:00 2001 From: Nicolas Benech Date: Mon, 27 Aug 2018 10:56:19 -0400 Subject: gpu: nvgpu: Fix nvgpu_readl MISRA 17.7 violations MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_readl. JIRA NVGPU-677 Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0 Signed-off-by: Nicolas Benech Reviewed-on: https://git-master.nvidia.com/r/1807528 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/clk_gp106.c | 8 ++++---- drivers/gpu/nvgpu/gp106/mclk_gp106.c | 4 ++-- drivers/gpu/nvgpu/gp106/pmu_gp106.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106') diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 13a401f0..e892ceda 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c @@ -188,7 +188,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); /* Force wb() */ - gk20a_readl(g, c->cntr.reg_ctrl_addr); + (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); /* Wait for reset to happen */ retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; @@ -209,7 +209,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | c->cntr.reg_ctrl_idx); - gk20a_readl(g, c->cntr.reg_ctrl_addr); + (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); nvgpu_udelay(XTAL_CNTR_DELAY); @@ -220,9 +220,9 @@ read_err: gk20a_writel(g, c->cntr.reg_ctrl_addr, trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); - gk20a_readl(g, c->cntr.reg_ctrl_addr); + (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); - gk20a_readl(g, c->cntr.reg_ctrl_addr); + (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); nvgpu_mutex_release(&clk->clk_mutex); return cntr; diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c index 36092a1a..6a49e83b 100644 --- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c @@ -3371,8 +3371,8 @@ int gp106_mclk_change(struct gk20a *g, u16 val) if (speed == GP106_MCLK_HIGH_SPEED) { gk20a_writel(g, 0x132000, 0x98010000); /* Introduce delay */ - gk20a_readl(g, 0x132000); - gk20a_readl(g, 0x132000); + (void) gk20a_readl(g, 0x132000); + (void) gk20a_readl(g, 0x132000); } gk20a_writel(g, 0x137300, 0x20000103); diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 963668c4..031ac7d8 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c @@ -71,11 +71,11 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset) if (do_reset) { gk20a_writel(g, pwr_falcon_engine_r(), pwr_falcon_engine_reset_false_f()); - gk20a_readl(g, pwr_falcon_engine_r()); + (void) gk20a_readl(g, pwr_falcon_engine_r()); } else { gk20a_writel(g, pwr_falcon_engine_r(), pwr_falcon_engine_reset_true_f()); - gk20a_readl(g, pwr_falcon_engine_r()); + (void) gk20a_readl(g, pwr_falcon_engine_r()); } return 0; -- cgit v1.2.2