From e13d0723f62a0cfa5a2a1b007e08cfe3788a143a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 27 Apr 2017 10:48:59 -0700 Subject: gpu: nvgpu: Use correct register for ROM control We access ROM control register with xve_writel, but we also add the base register address. This leads to adding the base address twice, and the access goes to wrong register. Bug 1846641 Change-Id: I46ef277aac661a08049935b08505120cad1a5e76 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1471505 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp106/xve_gp106.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106/xve_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c index 4d00b20b..2bd93666 100644 --- a/drivers/gpu/nvgpu/gp106/xve_gp106.c +++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c @@ -670,13 +670,13 @@ static void xve_rearm_msi_gp106(struct gk20a *g) static void xve_enable_shadow_rom_gp106(struct gk20a *g) { - g->ops.xve.xve_writel(g, NV_PCFG + xve_rom_ctrl_r(), + g->ops.xve.xve_writel(g, xve_rom_ctrl_r(), xve_rom_ctrl_rom_shadow_enabled_f()); } static void xve_disable_shadow_rom_gp106(struct gk20a *g) { - g->ops.xve.xve_writel(g, NV_PCFG + xve_rom_ctrl_r(), + g->ops.xve.xve_writel(g, xve_rom_ctrl_r(), xve_rom_ctrl_rom_shadow_disabled_f()); } -- cgit v1.2.2