From 2f712e22303471b8dd2f9388c874d12b07aed258 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 28 Jun 2017 16:23:18 +0530 Subject: gpu: nvgpu: falcon HAL to support SEC2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Updated falcon controller HAL to support SEC2 falcon & used "is_falcon_supported" flag to know the support on chip. - Created falcon HAL “flcn_gp106.c/h” under gp106 to enable support for SEC2 & inherited gk20a flcn support. - Deleted SEC2 falcon related methods to make use of generic flacon controller methods for SEC2. - GP106 SEC2 code cleanup NVPU JIRA-99 Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1510200 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 116 ++--------------------------------- 1 file changed, 4 insertions(+), 112 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index f49d56c4..06f62a99 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -90,57 +90,6 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) return completion; } -void sec2_copy_to_dmem(struct nvgpu_pmu *pmu, - u32 dst, u8 *src, u32 size, u8 port) -{ - struct gk20a *g = gk20a_from_pmu(pmu); - u32 i, words, bytes; - u32 data, addr_mask; - u32 *src_u32 = (u32*)src; - - if (size == 0) { - nvgpu_err(g, "size is zero"); - return; - } - - if (dst & 0x3) { - nvgpu_err(g, "dst (0x%08x) not 4-byte aligned", dst); - return; - } - - nvgpu_mutex_acquire(&pmu->pmu_copy_lock); - - words = size >> 2; - bytes = size & 0x3; - - addr_mask = psec_falcon_dmemc_offs_m() | - psec_falcon_dmemc_blk_m(); - - dst &= addr_mask; - - gk20a_writel(g, psec_falcon_dmemc_r(port), - dst | psec_falcon_dmemc_aincw_f(1)); - - for (i = 0; i < words; i++) - gk20a_writel(g, psec_falcon_dmemd_r(port), src_u32[i]); - - if (bytes > 0) { - data = 0; - for (i = 0; i < bytes; i++) - ((u8 *)&data)[i] = src[(words << 2) + i]; - gk20a_writel(g, psec_falcon_dmemd_r(port), data); - } - - data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask; - size = ALIGN(size, 4); - if (data != dst + size) { - nvgpu_err(g, "copy failed. bytes written %d, expected %d", - data - dst, size); - } - nvgpu_mutex_release(&pmu->pmu_copy_lock); - return; -} - int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, void *desc, u32 bl_sz) { @@ -184,7 +133,7 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, psec_falcon_dmemc_offs_f(0) | psec_falcon_dmemc_blk_f(0) | psec_falcon_dmemc_aincw_f(1)); - sec2_copy_to_dmem(pmu, 0, (u8 *)desc, + nvgpu_flcn_copy_to_dmem(&g->sec2_flcn, 0, (u8 *)desc, sizeof(struct flcn_bl_dmem_desc), 0); /*TODO This had to be copied to bl_desc_dmem_load_off, but since * this is 0, so ok for now*/ @@ -225,61 +174,6 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, return 0; } -void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable) -{ - struct gk20a *g = gk20a_from_pmu(pmu); - - gk20a_dbg_fn(""); - - gk20a_writel(g, psec_falcon_irqmclr_r(), - psec_falcon_irqmclr_gptmr_f(1) | - psec_falcon_irqmclr_wdtmr_f(1) | - psec_falcon_irqmclr_mthd_f(1) | - psec_falcon_irqmclr_ctxsw_f(1) | - psec_falcon_irqmclr_halt_f(1) | - psec_falcon_irqmclr_exterr_f(1) | - psec_falcon_irqmclr_swgen0_f(1) | - psec_falcon_irqmclr_swgen1_f(1) | - psec_falcon_irqmclr_ext_f(0xff)); - - if (enable) { - /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */ - gk20a_writel(g, psec_falcon_irqdest_r(), - psec_falcon_irqdest_host_gptmr_f(0) | - psec_falcon_irqdest_host_wdtmr_f(1) | - psec_falcon_irqdest_host_mthd_f(0) | - psec_falcon_irqdest_host_ctxsw_f(0) | - psec_falcon_irqdest_host_halt_f(1) | - psec_falcon_irqdest_host_exterr_f(0) | - psec_falcon_irqdest_host_swgen0_f(1) | - psec_falcon_irqdest_host_swgen1_f(0) | - psec_falcon_irqdest_host_ext_f(0xff) | - psec_falcon_irqdest_target_gptmr_f(1) | - psec_falcon_irqdest_target_wdtmr_f(0) | - psec_falcon_irqdest_target_mthd_f(0) | - psec_falcon_irqdest_target_ctxsw_f(0) | - psec_falcon_irqdest_target_halt_f(0) | - psec_falcon_irqdest_target_exterr_f(0) | - psec_falcon_irqdest_target_swgen0_f(0) | - psec_falcon_irqdest_target_swgen1_f(1) | - psec_falcon_irqdest_target_ext_f(0xff)); - - /* 0=disable, 1=enable */ - gk20a_writel(g, psec_falcon_irqmset_r(), - psec_falcon_irqmset_gptmr_f(1) | - psec_falcon_irqmset_wdtmr_f(1) | - psec_falcon_irqmset_mthd_f(0) | - psec_falcon_irqmset_ctxsw_f(0) | - psec_falcon_irqmset_halt_f(1) | - psec_falcon_irqmset_exterr_f(1) | - psec_falcon_irqmset_swgen0_f(1) | - psec_falcon_irqmset_swgen1_f(1)); - - } - - gk20a_dbg_fn("done"); -} - void init_pmu_setup_hw1(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -330,7 +224,7 @@ void init_pmu_setup_hw1(struct gk20a *g) } -static int gp106_sec2_reset(struct gk20a *g) +int gp106_sec2_reset(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -351,9 +245,9 @@ int init_sec2_setup_hw1(struct gk20a *g, int err; u32 data = 0; - gk20a_dbg_fn(""); + nvgpu_log_fn(g, " "); - gp106_sec2_reset(g); + nvgpu_flcn_reset(&g->sec2_flcn); data = gk20a_readl(g, psec_fbif_ctl_r()); data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f(); @@ -380,8 +274,6 @@ int init_sec2_setup_hw1(struct gk20a *g, psec_fbif_transcfg_mem_type_physical_f() | psec_fbif_transcfg_target_noncoherent_sysmem_f()); - /*disable irqs for hs falcon booting as we will poll for halt*/ - sec_enable_irq(pmu, false); err = bl_bootstrap_sec2(pmu, desc, bl_sz); if (err) return err; -- cgit v1.2.2