From a69fa0e96cb8ca253ec3468f288f410219129b9a Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 11 Jan 2017 09:53:29 +0530 Subject: nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL. pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/pmu_gp106.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gp106/pmu_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 8d552a5b..9aac5328 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c @@ -317,6 +317,10 @@ void gp106_init_pmu_ops(struct gpu_ops *gops) gops->pmu.init_wpr_region = NULL; } gops->pmu.pmu_setup_elpg = NULL; + gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; + gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; + gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; + gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; gops->pmu.lspmuwprinitdone = 0; gops->pmu.fecsbootstrapdone = false; gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; -- cgit v1.2.2