From 27694ca572c4d7698b107c6713f0f0604b41c186 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 25 May 2018 10:27:10 -0700 Subject: gpu: nvgpu: Implement bus HAL for bar2 bind Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL. BAR2 bind HW API is in bus. JIRA NVGPU-588 Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730896 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index eec0f917..f35abac7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -26,6 +26,7 @@ #include "common/clock_gating/gp106_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/bus/bus_gm20b.h" +#include "common/bus/bus_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -583,7 +584,6 @@ static const struct gpu_ops gp106_ops = { .init_inst_block = gk20a_init_inst_block, .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, .remove_bar2_vm = gp10b_remove_bar2_vm, .get_vidmem_size = gp106_mm_get_vidmem_size, .get_kind_invalid = gm20b_get_kind_invalid, @@ -723,6 +723,7 @@ static const struct gpu_ops gp106_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .bar1_bind = gm20b_bus_bar1_bind, + .bar2_bind = gp10b_bus_bar2_bind, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { -- cgit v1.2.2