From 3d0f9a751784ac9eb27f9f989f3b584ff5dc8f17 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 23 Mar 2016 08:41:04 -0700 Subject: gpu: nvgpu: Add support for gp104 and gp106 Add support for chips gp104 and gp106. Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1120465 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gp106/gr_gp106.c | 111 +++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp106/gr_gp106.c (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c new file mode 100644 index 00000000..e4768e0d --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -0,0 +1,111 @@ +/* + * GP106 GPU GR + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ + +#include "gk20a/gr_gk20a.h" + +#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ +#include "gp10b/gr_gp10b.h" +#include "gr_gp106.h" +#include "hw_gr_gp106.h" + +static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num) +{ + bool valid = false; + + switch (class_num) { + case PASCAL_COMPUTE_A: + case PASCAL_COMPUTE_B: + case PASCAL_A: + case PASCAL_B: + case PASCAL_DMA_COPY_A: + valid = true; + break; + + case MAXWELL_COMPUTE_B: + case MAXWELL_B: + case FERMI_TWOD_A: + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + valid = true; + break; + + default: + break; + } + gk20a_dbg_info("class=0x%x valid=%d", class_num, valid); + return valid; +} + +static u32 gr_gp106_pagepool_default_size(struct gk20a *g) +{ + return gr_scc_pagepool_total_pages_hwmax_value_v(); +} + +static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data) +{ + gk20a_dbg_fn(""); + + if (class_num == PASCAL_COMPUTE_B) { + switch (offset << 2) { + case NVC0C0_SET_SHADER_EXCEPTIONS: + gk20a_gr_set_shader_exceptions(g, data); + break; + default: + goto fail; + } + } + + if (class_num == PASCAL_B) { + switch (offset << 2) { + case NVC097_SET_SHADER_EXCEPTIONS: + gk20a_gr_set_shader_exceptions(g, data); + break; + case NVC097_SET_CIRCULAR_BUFFER_SIZE: + g->ops.gr.set_circular_buffer_size(g, data); + break; + case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: + g->ops.gr.set_alpha_circular_buffer_size(g, data); + break; + default: + goto fail; + } + } + return 0; + +fail: + return -EINVAL; +} + +static void gr_gp106_cb_size_default(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + if (!gr->attrib_cb_default_size) + gr->attrib_cb_default_size = 0x800; + gr->alpha_cb_default_size = + gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); +} + +void gp106_init_gr(struct gpu_ops *gops) +{ + gp10b_init_gr(gops); + gops->gr.is_valid_class = gr_gp106_is_valid_class; + gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size; + gops->gr.handle_sw_method = gr_gp106_handle_sw_method; + gops->gr.cb_size_default = gr_gp106_cb_size_default; +} -- cgit v1.2.2 From 454cb1631be1a09b25c45a18a97fdaae2f5cdf76 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Fri, 17 Jun 2016 12:40:54 +0530 Subject: gpu: nvgpu: Add new CE class for gp10x Added new CE class(PASCAL_DMA_COPY_B) for gp106 and gp104. JIRA DNVGPU-25 Change-Id: I3c85e3ffdedf7594d41bf5c2fbebbf44addd1720 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1166709 Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp106/gr_gp106.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index e4768e0d..d54a2089 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -32,6 +32,7 @@ static bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num) case PASCAL_A: case PASCAL_B: case PASCAL_DMA_COPY_A: + case PASCAL_DMA_COPY_B: valid = true; break; -- cgit v1.2.2 From b583ef729636677c86651685a392849bb8e22431 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 7 Jul 2016 04:03:44 -0700 Subject: gpu: nvgpu: Disable init_preemption_state on dGPU Discrete GPU does not have clocks wired correctly. They're needed to be able to calculate correct preemption timeout, so disable setting the timeout. Change-Id: I14a6d262f6b004d40432a4e026c5558303aa90a4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1176904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman Reviewed-by: Mahantesh Kumbar Tested-by: Mahantesh Kumbar GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp106/gr_gp106.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index d54a2089..9d6ce6ec 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -109,4 +109,5 @@ void gp106_init_gr(struct gpu_ops *gops) gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size; gops->gr.handle_sw_method = gr_gp106_handle_sw_method; gops->gr.cb_size_default = gr_gp106_cb_size_default; + gops->gr.init_preemption_state = NULL; } -- cgit v1.2.2 From cae5d380d8b465f4d1389ae80d6cec1458951e29 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 28 Jul 2016 16:53:31 +0530 Subject: gpu: nvgpu: Add preemption mode support for gp10x Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x family gr class (PASCAL_B and PASCAL_COMPUTE_B). Bug 200221149 Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1193209 Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp106/gr_gp106.c | 118 +++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index 9d6ce6ec..01d06975 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -102,6 +102,123 @@ static void gr_gp106_cb_size_default(struct gk20a *g) gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } +static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, + struct gr_ctx_desc *gr_ctx, + struct vm_gk20a *vm, u32 class, + u32 graphics_preempt_mode, + u32 compute_preempt_mode) +{ + int err = 0; + + if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp) + graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; + + if (class == PASCAL_COMPUTE_B && + g->gr.t18x.ctx_vars.force_preemption_cilp) + compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; + + /* check for invalid combinations */ + if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) + return -EINVAL; + + if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) && + (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP)) + return -EINVAL; + + /* set preemption modes */ + switch (graphics_preempt_mode) { + case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP: + { + u32 spill_size = + gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); + u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); + u32 betacb_size = g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count; + attrib_cb_size = ALIGN(attrib_cb_size, 128); + + gk20a_dbg_info("gfxp context spill_size=%d", spill_size); + gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size); + gk20a_dbg_info("gfxp context attrib_cb_size=%d", + attrib_cb_size); + + err = gr_gp10b_alloc_buffer(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &gr_ctx->t18x.preempt_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(g), + "cannot allocate preempt buffer"); + goto fail; + } + + err = gr_gp10b_alloc_buffer(vm, + spill_size, + &gr_ctx->t18x.spill_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(g), + "cannot allocate spill buffer"); + goto fail_free_preempt; + } + + err = gr_gp10b_alloc_buffer(vm, + attrib_cb_size, + &gr_ctx->t18x.betacb_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(g), + "cannot allocate beta buffer"); + goto fail_free_spill; + } + + err = gr_gp10b_alloc_buffer(vm, + pagepool_size, + &gr_ctx->t18x.pagepool_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(g), + "cannot allocate page pool"); + goto fail_free_betacb; + } + + gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + break; + } + + case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI: + gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + break; + + default: + break; + } + + if (class == PASCAL_COMPUTE_B) { + switch (compute_preempt_mode) { + case NVGPU_COMPUTE_PREEMPTION_MODE_WFI: + case NVGPU_COMPUTE_PREEMPTION_MODE_CTA: + case NVGPU_COMPUTE_PREEMPTION_MODE_CILP: + gr_ctx->compute_preempt_mode = compute_preempt_mode; + break; + default: + break; + } + } + + return 0; + +fail_free_betacb: + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); +fail_free_spill: + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); +fail_free_preempt: + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); +fail: + return err; +} + void gp106_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -110,4 +227,5 @@ void gp106_init_gr(struct gpu_ops *gops) gops->gr.handle_sw_method = gr_gp106_handle_sw_method; gops->gr.cb_size_default = gr_gp106_cb_size_default; gops->gr.init_preemption_state = NULL; + gops->gr.set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode; } -- cgit v1.2.2 From 190e97f89bd486363db9916967a173e0bde5f43b Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Wed, 10 Aug 2016 21:57:30 +0300 Subject: gpu: nvgpu: gp106: Add NVC097_SET_GO_IDLE_TIMEOUT SW method Add the NVC097_SET_GO_IDLE_TIMEOUT SW method for GP106. This enables booting the X server. Bug 1732372 Bug 1792002 Change-Id: I73abaaea240039dc91c66e3862ec01a342db2fa9 Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/1200637 (cherry picked from commit 0d24a6f3d8e421ea5205279166c6dc2d0f15c6a0) Reviewed-on: http://git-master/r/1223101 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp106/gr_gp106.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index 01d06975..8d8376d3 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -56,6 +56,11 @@ static u32 gr_gp106_pagepool_default_size(struct gk20a *g) return gr_scc_pagepool_total_pages_hwmax_value_v(); } +static void gr_gp106_set_go_idle_timeout(struct gk20a *g, u32 data) +{ + gk20a_writel(g, gr_fe_go_idle_timeout_r(), data); +} + static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { @@ -82,6 +87,9 @@ static int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr, case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_alpha_circular_buffer_size(g, data); break; + case NVC097_SET_GO_IDLE_TIMEOUT: + gr_gp106_set_go_idle_timeout(g, data); + break; default: goto fail; } -- cgit v1.2.2