From 2f712e22303471b8dd2f9388c874d12b07aed258 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 28 Jun 2017 16:23:18 +0530 Subject: gpu: nvgpu: falcon HAL to support SEC2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Updated falcon controller HAL to support SEC2 falcon & used "is_falcon_supported" flag to know the support on chip. - Created falcon HAL “flcn_gp106.c/h” under gp106 to enable support for SEC2 & inherited gk20a flcn support. - Deleted SEC2 falcon related methods to make use of generic flacon controller methods for SEC2. - GP106 SEC2 code cleanup NVPU JIRA-99 Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1510200 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp106/flcn_gp106.c | 85 ++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp106/flcn_gp106.c (limited to 'drivers/gpu/nvgpu/gp106/flcn_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/flcn_gp106.c b/drivers/gpu/nvgpu/gp106/flcn_gp106.c new file mode 100644 index 00000000..6ae0b7af --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/flcn_gp106.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#include "gk20a/gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gp106/sec2_gp106.h" + +#include + +static void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) +{ + struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = + &flcn->flcn_engine_dep_ops; + + switch (flcn->flcn_id) { + case FALCON_ID_PMU: + flcn_eng_dep_ops->reset_eng = nvgpu_pmu_reset; + break; + case FALCON_ID_SEC2: + flcn_eng_dep_ops->reset_eng = gp106_sec2_reset; + break; + default: + flcn_eng_dep_ops->reset_eng = NULL; + break; + } +} + +static void gp106_falcon_ops(struct nvgpu_falcon *flcn) +{ + gk20a_falcon_ops(flcn); + gp106_falcon_engine_dependency_ops(flcn); +} + +static void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn) +{ + struct gk20a *g = flcn->g; + + switch (flcn->flcn_id) { + case FALCON_ID_PMU: + flcn->flcn_base = FALCON_PWR_BASE; + flcn->is_falcon_supported = true; + flcn->is_interrupt_enabled = true; + break; + case FALCON_ID_SEC2: + flcn->flcn_base = FALCON_SEC_BASE; + flcn->is_falcon_supported = true; + flcn->is_interrupt_enabled = false; + break; + case FALCON_ID_FECS: + flcn->flcn_base = FALCON_FECS_BASE; + flcn->is_falcon_supported = true; + flcn->is_interrupt_enabled = false; + break; + case FALCON_ID_GPCCS: + flcn->flcn_base = FALCON_GPCCS_BASE; + flcn->is_falcon_supported = true; + flcn->is_interrupt_enabled = false; + break; + default: + flcn->is_falcon_supported = false; + nvgpu_err(g, "Invalid flcn request"); + break; + } + + if (flcn->is_falcon_supported) { + nvgpu_mutex_init(&flcn->copy_lock); + gp106_falcon_ops(flcn); + } else + nvgpu_info(g, "falcon 0x%x not supported on %s", + flcn->flcn_id, g->name); +} + +void gp106_falcon_init_hal(struct gpu_ops *gops) +{ + gops->falcon.falcon_hal_sw_init = gp106_falcon_hal_sw_init; +} -- cgit v1.2.2