From bc05e0e0e5b7d00761472252e9f8c12886539746 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Jun 2018 12:44:04 +0530 Subject: gpu: nvgpu: SEC2 reset using common falcon HAL -Do sec2 reset using common falcon HAL nvgpu_flcn_reset() by passing sec2_flcn struct which holds base address of SEC2 falcon as per chip specific. JIRA NVGPUT-111 Change-Id: I2b95262a93644bbefed5b6c46dc73200afd97730 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1755617 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp106/acr_gp106.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gp106/acr_gp106.c') diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 35940b97..5cffc69b 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c @@ -1297,11 +1297,7 @@ int gp106_bootstrap_hs_flcn(struct gk20a *g) } /* sec2 reset - to keep it idle */ - gk20a_writel(g, psec_falcon_engine_r(), - pwr_falcon_engine_reset_true_f()); - nvgpu_udelay(10); - gk20a_writel(g, psec_falcon_engine_r(), - pwr_falcon_engine_reset_false_f()); + nvgpu_flcn_reset(&g->sec2_flcn); return 0; err_free_ucode_map: -- cgit v1.2.2