From e98ac1867deb5acf008b8400ea78e81986719df7 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Tue, 30 Sep 2014 23:19:50 -0700 Subject: gpu: nvgpu: Update GM20b GPCPLL NA mode settings - Updated DFS_COEFF slope/intercept parameters - Specified VCO control gain - Increased safe DVFS margin to 10% Bug 1555318 Change-Id: I619704b7ba029d77ea1019a86003c3e8d80d04d8 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/552446 Reviewed-by: Yu-Huan Hsu --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 16f88d62..eb7703bd 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -43,7 +43,7 @@ #define BOOT_GPU_UV 1000000 /* gpu rail boot voltage 1.0V */ #define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */ -#define DVFS_SAFE_MARGIN 8 /* 8% */ +#define DVFS_SAFE_MARGIN 10 /* 10% */ static unsigned long dvfs_safe_max_freq; static struct pll_parms gpc_pll_params = { @@ -53,9 +53,9 @@ static struct pll_parms gpc_pll_params = { 1, 255, /* M */ 8, 255, /* N */ 1, 31, /* PL */ - -58700, 86789, /* DFS_COEFF */ + -165230, 214007, /* DFS_COEFF */ 0, 0, /* ADC char coeff - to be read from fuses */ - 0, /* FIXME: vco control data */ + 0x7 << 3, /* vco control in NA mode */ }; #ifdef CONFIG_DEBUG_FS -- cgit v1.2.2