From e16843c2efdffa13c15cc0a014b2a5598cc2f4ec Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 21 Sep 2018 12:06:36 +0530 Subject: gpu: nvgpu: read GPC mask from h/w In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate GPC mask in s/w and return to user space But this could give incorrect result as any GPC could be floorswept in h/w Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status from fuse Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w Set these HALs only for dGPUs right now. Fuse register to read GPC mask is not yet supported in simulation and hence simulation boot fails These HALs will be set for iGPU once simulation issue is resolved Use gops.gr.get_gpc_mask() if it is defined in gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask to user space Jira NVGPUT-132 Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1822811 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 17 +++++++++++++++++ drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 1 + 2 files changed, 18 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 368c9321..c67f7870 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -550,6 +550,23 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); } +u32 gr_gm20b_get_gpc_mask(struct gk20a *g) +{ + u32 val; + struct gr_gk20a *gr = &g->gr; + + /* + * For register NV_FUSE_STATUS_OPT_GPC a set bit with index i indicates + * corresponding GPC is floorswept + * But for s/w mask a set bit means GPC is enabled and it is disabled + * otherwise + * Hence toggle the bits of register value to get s/w mask + */ + val = g->ops.fuse.fuse_status_opt_gpc(g); + + return (~val) & (BIT32(gr->max_gpc_count) - 1U); +} + u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { u32 val; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 7402478d..084b6157 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -83,6 +83,7 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, u32 *ctrl_register_stride); u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +u32 gr_gm20b_get_gpc_mask(struct gk20a *g); void gr_gm20b_load_tpc_mask(struct gk20a *g); void gr_gm20b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); -- cgit v1.2.2