From d59271c7b79080388371877fc2d10574ca42206a Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 24 Jul 2017 12:18:38 -0700 Subject: gpu: nvgpu: Remove privsecurity flag from gpu_ops Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 10 ++++++---- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 2 +- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 16 ++++++++-------- drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 7 +++++-- drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 6 ++++-- 5 files changed, 24 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 5d9cc32c..f60d880d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -42,7 +42,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) gk20a_dbg_info("initialize gpc mmu"); - if (!g->ops.privsecurity) { + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Bypass MMU check for non-secure boot. For * secure-boot,this register write has no-effect */ gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); @@ -680,7 +680,7 @@ static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, gr_gk20a_load_ctxsw_ucode_boot(g, addr_base, segments, reg_offset); /* start the falcon immediately if PRIV security is disabled*/ - if (!g->ops.privsecurity) { + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { gk20a_writel(g, reg_offset + gr_fecs_cpuctl_r(), gr_fecs_cpuctl_startcpu_f(0x01)); } @@ -1542,8 +1542,10 @@ static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); } -void gm20b_init_gr(struct gpu_ops *gops) +void gm20b_init_gr(struct gk20a *g) { + struct gpu_ops *gops = &g->ops; + gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; gops->gr.cb_size_default = gr_gm20b_cb_size_default; @@ -1565,7 +1567,7 @@ void gm20b_init_gr(struct gpu_ops *gops) gops->gr.init_fs_state = gr_gm20b_init_fs_state; gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; - if (gops->privsecurity) + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; else gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index e7dd091a..d3adacd8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -36,7 +36,7 @@ enum { #define NVB1C0_SET_RD_COALESCE 0x0228 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -void gm20b_init_gr(struct gpu_ops *gops); +void gm20b_init_gr(struct gk20a *g); void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, bool patch); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 01e277ce..228e1a97 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -356,38 +356,38 @@ int gm20b_init_hal(struct gk20a *g) #ifdef CONFIG_TEGRA_ACR if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); } else { val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); if (!val) { gk20a_dbg_info("priv security is disabled in HW"); - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); } else { - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); } } #else if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { gk20a_dbg_info("running ASIM with PRIV security disabled"); - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); } else { val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); if (!val) { - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); } else { gk20a_dbg_info("priv security is not supported but enabled"); - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); return -EPERM; } } #endif g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; - gm20b_init_gr(gops); + gm20b_init_gr(g); gm20b_init_fb(gops); gm20b_init_ce2(gops); gm20b_init_gr_ctx(gops); gm20b_init_mm(gops); - gm20b_init_pmu_ops(gops); + gm20b_init_pmu_ops(g); gm20b_init_clk_ops(gops); gm20b_init_regops(gops); gm20b_init_therm_ops(gops); diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 0f99c67e..98cd3906 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -273,9 +274,11 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) val); } -void gm20b_init_pmu_ops(struct gpu_ops *gops) +void gm20b_init_pmu_ops(struct gk20a *g) { - if (gops->privsecurity) { + struct gpu_ops *gops = &g->ops; + + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index e3deb6ef..424fab35 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B PMU * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,7 +16,9 @@ #ifndef __PMU_GM20B_H_ #define __PMU_GM20B_H_ -void gm20b_init_pmu_ops(struct gpu_ops *gops); +struct gk20a; + +void gm20b_init_pmu_ops(struct gk20a *g); void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); int gm20b_pmu_init_acr(struct gk20a *g); void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); -- cgit v1.2.2