From b8efd9d04537d6129e2ce8b067417e46b0e7436f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 27 Jul 2017 12:58:03 -0700 Subject: gpu: nvgpu: Make LTC disabling common code Refactor the sync_debugfs LTC HAL op so that the logic to enable or disable LTC goes to common code nvgpu_ltc_sync_enabled() and the LTC HAL set_enabled only performs the hardware register access. Create a new common function nvgpu_init_ltc_support() to initialize the LTC software variable, and move hardware initialization of LTC to be called from it. JIRA NVGPU-62 Change-Id: Ib1cf4f5b83ca3dac08407464ed56a732e0a33923 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1528262 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 +--- drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 26 +++++++++----------------- drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | 4 +--- 3 files changed, 11 insertions(+), 23 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c16cd3e5..7861e438 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -155,9 +155,7 @@ static const struct gpu_ops gm20b_ops = { .isr = gm20b_ltc_isr, .cbc_fix_config = gm20b_ltc_cbc_fix_config, .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gm20b_ltc_sync_debugfs, -#endif + .set_enabled = gm20b_ltc_set_enabled, }, .ce2 = { .isr_stall = gk20a_ce2_isr, diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 5e938141..6fef01ea 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c @@ -437,25 +437,17 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) } -#ifdef CONFIG_DEBUG_FS -void gm20b_ltc_sync_debugfs(struct gk20a *g) +void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled) { u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); + u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); - nvgpu_spinlock_acquire(&g->debugfs_lock); - if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { - u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); - - if (g->mm.ltc_enabled_debug) - /* bypass disabled (normal caching ops)*/ - reg &= ~reg_f; - else - /* bypass enabled (no caching) */ - reg |= reg_f; + if (enabled) + /* bypass disabled (normal caching ops)*/ + reg &= ~reg_f; + else + /* bypass enabled (no caching) */ + reg |= reg_f; - gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); - g->mm.ltc_enabled = g->mm.ltc_enabled_debug; - } - nvgpu_spinlock_release(&g->debugfs_lock); + gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); } -#endif diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h index 3b4b16e3..bfd501d6 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h @@ -26,9 +26,7 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, struct zbc_entry *depth_val, u32 index); void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); -#ifdef CONFIG_DEBUG_FS -void gm20b_ltc_sync_debugfs(struct gk20a *g); -#endif +void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled); void gm20b_ltc_init_fs_state(struct gk20a *g); int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, u32 min, u32 max); -- cgit v1.2.2