From a6108a4b0ed52c7a8fa58d9815d0b373be8305bf Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Tue, 28 Aug 2018 18:13:28 -0700 Subject: gpu: nvgpu: Fix GM20b GPCPLL debugfs node GM20B GPCPLL registers are accessed via sys address space with the exception of the last dvfs2 register that can be accessed only through bcast address. However, in debugfs loop dvfs2 sys address should be used as loop terminator; otherwise, loop body is never executed, and GPCPLL registers debugfs node is broken. Fixed it in this commit. Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0 Signed-off-by: Alex Frid Reviewed-on: https://git-master.nvidia.com/r/1808784 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 3 ++- drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 93bae921..2ba677b0 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -1655,7 +1655,8 @@ int gm20b_clk_get_pll_debug_data(struct gk20a *g, d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r(); d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r()); d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r(); - d->trim_sys_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r(); + d->trim_sys_gpcpll_dvfs2_reg = trim_sys_gpcpll_dvfs2_r(); + d->trim_bcast_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r(); reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); d->trim_sys_gpcpll_cfg_val = reg; diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index e814ac70..c93d4ee3 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h @@ -41,6 +41,7 @@ struct nvgpu_clk_pll_debug_data { u32 trim_sys_gpcpll_cfg_reg; u32 trim_sys_gpcpll_dvfs2_reg; + u32 trim_bcast_gpcpll_dvfs2_reg; u32 trim_sys_gpcpll_cfg_val; bool trim_sys_gpcpll_cfg_enabled; -- cgit v1.2.2