From 9a28bab63fc99146ba2f356bab861d2a59cce115 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Tue, 22 Aug 2017 22:33:59 -0700 Subject: gpu: nvgpu: Use bcast bank to debug GM20B dvfs2 GM20B GPCPLL dvfs register cannot be accessed through sys registers bank (as other PLL registers), instead bcast bank must be used. This limitation was already taken into account for production access, but dbugfs access has incorrectly used sys bank. Fixed bank access in this commit. Change-Id: Ic7ca640c586addea3aaae4f10a98af8497d6f3cb Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/1504241 Reviewed-on: https://git-master.nvidia.com/r/1543854 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Krishna Reddy --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 81f8aec0..a13f943a 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -1539,6 +1539,9 @@ int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val) (reg != trim_sys_bypassctrl_r())) return -EPERM; + if (reg == trim_sys_gpcpll_dvfs2_r()) + reg = trim_gpc_bcast_gpcpll_dvfs2_r(); + nvgpu_mutex_acquire(&g->clk.clk_mutex); if (!g->clk.clk_hw_on) { nvgpu_mutex_release(&g->clk.clk_mutex); @@ -1568,7 +1571,7 @@ int gm20b_clk_get_pll_debug_data(struct gk20a *g, d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r(); d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r()); d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r(); - d->trim_sys_gpcpll_dvfs2_reg = trim_sys_gpcpll_dvfs2_r(); + d->trim_sys_gpcpll_dvfs2_reg = trim_gpc_bcast_gpcpll_dvfs2_r(); reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); d->trim_sys_gpcpll_cfg_val = reg; -- cgit v1.2.2