From 2d5ff668cbc6a932df2c9cf79627d1d340e5c2c0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 11:06:59 +0200 Subject: gpu: nvgpu: GR and LTC HAL to use const structs Convert GR and LTC HALs to use const structs, and initialize them with macros. Bug 1567274 Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/590371 --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 91 +++++++++++++++------------------- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 8 +-- drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h | 79 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 38 +++++++------- 4 files changed, 144 insertions(+), 72 deletions(-) create mode 100644 drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 8a3de4e8..7b69c5c8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1,5 +1,5 @@ /* - * GM20B GPC MMU + * GM20B GPU GR * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. * @@ -16,6 +16,7 @@ #include #include /* for mdelay */ +#include "gr_ops.h" #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" @@ -28,7 +29,7 @@ #include "pmu_gm20b.h" #include "acr_gm20b.h" -static void gr_gm20b_init_gpc_mmu(struct gk20a *g) +void gr_gm20b_init_gpc_mmu(struct gk20a *g) { u32 temp; @@ -64,7 +65,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); } -static void gr_gm20b_bundle_cb_defaults(struct gk20a *g) +void gr_gm20b_bundle_cb_defaults(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -76,7 +77,7 @@ static void gr_gm20b_bundle_cb_defaults(struct gk20a *g) gr_pd_ab_dist_cfg2_token_limit_init_v(); } -static void gr_gm20b_cb_size_default(struct gk20a *g) +void gr_gm20b_cb_size_default(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -86,7 +87,7 @@ static void gr_gm20b_cb_size_default(struct gk20a *g) gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } -static int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) +int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; int size; @@ -107,7 +108,7 @@ static int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) return size; } -static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g, +void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, bool patch) { @@ -124,7 +125,7 @@ static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); } -static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, +void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, u64 size, bool patch) { @@ -160,7 +161,7 @@ static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, } -static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, +int gr_gm20b_commit_global_cb_manager(struct gk20a *g, struct channel_gk20a *c, bool patch) { struct gr_gk20a *gr = &g->gr; @@ -247,7 +248,7 @@ static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, return 0; } -static void gr_gm20b_commit_global_pagepool(struct gk20a *g, +void gr_gm20b_commit_global_pagepool(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, u32 size, bool patch) { @@ -259,7 +260,7 @@ static void gr_gm20b_commit_global_pagepool(struct gk20a *g, } -static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, +int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { gk20a_dbg_fn(""); @@ -280,10 +281,10 @@ static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, gk20a_gr_set_shader_exceptions(g, data); break; case NVB197_SET_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_circular_buffer_size(g, data); + g->ops.gr->set_circular_buffer_size(g, data); break; case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_alpha_circular_buffer_size(g, data); + g->ops.gr->set_alpha_circular_buffer_size(g, data); break; default: goto fail; @@ -295,7 +296,7 @@ fail: return -EINVAL; } -static void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) +void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) { struct gr_gk20a *gr = &g->gr; u32 gpc_index, ppc_index, stride, val; @@ -395,7 +396,7 @@ void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data) } } -static void gr_gm20b_enable_hww_exceptions(struct gk20a *g) +void gr_gm20b_enable_hww_exceptions(struct gk20a *g) { gr_gk20a_enable_hww_exceptions(g); @@ -406,7 +407,7 @@ static void gr_gm20b_enable_hww_exceptions(struct gk20a *g) gr_ds_hww_report_mask_2_sph24_err_report_f()); } -static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) +void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) { /* setup sm warp esr report masks */ gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), @@ -439,7 +440,7 @@ static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); } -static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) +bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -459,7 +460,7 @@ static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) return valid; } -static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, +void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, u32 *num_sm_dsm_perf_regs, u32 **sm_dsm_perf_regs, u32 *perf_register_stride) @@ -470,7 +471,7 @@ static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); } -static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, +void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, u32 *num_sm_dsm_perf_regs, u32 **sm_dsm_perf_regs, u32 *ctrl_register_stride) @@ -481,7 +482,7 @@ static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); } -static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { u32 val; struct gr_gk20a *gr = &g->gr; @@ -492,7 +493,7 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); } -static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g) +int gr_gm20b_init_fs_state(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; u32 tpc_index, gpc_index; @@ -595,7 +596,7 @@ static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g) return 0; } -static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, +int gr_gm20b_falcon_load_ucode(struct gk20a *g, u64 addr_base, struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset) { gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(), @@ -622,7 +623,7 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) gr_gk20a_load_falcon_bind_instblk(g); - g->ops.gr.falcon_load_ucode(g, addr_base, + g->ops.gr->falcon_load_ucode(g, addr_base, &g->ctxsw_ucode_info.gpccs, gr_gpcs_gpccs_falcon_hwcfg_r() - gr_fecs_falcon_hwcfg_r()); @@ -648,7 +649,7 @@ static int gr_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val) return -ETIMEDOUT; } -static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) +int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) { u32 err; gk20a_dbg_fn(""); @@ -710,42 +711,30 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) } #else -static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) +int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) { return -EPERM; } #endif +#include "gk20a/gr_ops_gk20a.h" +#include "gr_ops_gm20b.h" + +static struct gpu_gr_ops gm20b_gr_ops = { + __set_gr_gm20b_ops(), + __set_gr_gk20a_op(load_ctxsw_ucode) +}; + +static struct gpu_gr_ops gm20b_gr_privsecurity_ops = { + __set_gr_gm20b_ops(), + __set_gr_gm20b_op(load_ctxsw_ucode) +}; + void gm20b_init_gr(struct gpu_ops *gops) { - gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; - gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; - gops->gr.cb_size_default = gr_gm20b_cb_size_default; - gops->gr.calc_global_ctx_buffer_size = - gr_gm20b_calc_global_ctx_buffer_size; - gops->gr.commit_global_attrib_cb = gr_gk20a_commit_global_attrib_cb; - gops->gr.commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb; - gops->gr.commit_global_cb_manager = gr_gm20b_commit_global_cb_manager; - gops->gr.commit_global_pagepool = gr_gm20b_commit_global_pagepool; - gops->gr.handle_sw_method = gr_gm20b_handle_sw_method; - gops->gr.set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size; - gops->gr.set_circular_buffer_size = gr_gm20b_set_circular_buffer_size; - gops->gr.enable_hww_exceptions = gr_gm20b_enable_hww_exceptions; - gops->gr.is_valid_class = gr_gm20b_is_valid_class; - gops->gr.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs; - gops->gr.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs; - gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; - gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; - gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; if (gops->privsecurity) - gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; + gops->gr = &gm20b_gr_privsecurity_ops; else - gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; - gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; - gops->gr.free_channel_ctx = gk20a_free_channel_ctx; - gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; - gops->gr.free_obj_ctx = gk20a_free_obj_ctx; - gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; - gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; + gops->gr = &gm20b_gr_ops; } diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 8348b9d9..e822b33c 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -1,5 +1,5 @@ /* - * GM20B GPC MMU + * GM20B GPU GR * * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * @@ -13,8 +13,8 @@ * more details. */ -#ifndef _NVHOST_GM20B_GR_MMU_H -#define _NVHOST_GM20B_GR_MMU_H +#ifndef _NVGPU_GR_GM20B_H_ +#define _NVGPU_GR_GM20B_H_ struct gk20a; enum { @@ -29,5 +29,7 @@ enum { #define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 + +struct gpu_ops; void gm20b_init_gr(struct gpu_ops *gops); #endif diff --git a/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h new file mode 100644 index 00000000..9477da75 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h @@ -0,0 +1,79 @@ +/* + * GM20B GPU graphics ops + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _GR_OPS_GM20B_H_ +#define _GR_OPS_GM20B_H_ + +#include "gr_ops.h" + +#define __gr_gm20b_op(X) gr_gm20b_ ## X +#define __set_gr_gm20b_op(X) . X = gr_gm20b_ ## X + +void __gr_gm20b_op(init_gpc_mmu)(struct gk20a *); +void __gr_gm20b_op(bundle_cb_defaults)(struct gk20a *); +void __gr_gm20b_op(cb_size_default)(struct gk20a *); +int __gr_gm20b_op(calc_global_ctx_buffer_size)(struct gk20a *); +void __gr_gm20b_op(commit_global_bundle_cb)(struct gk20a *, + struct channel_ctx_gk20a *, u64, u64, bool); +int __gr_gm20b_op(commit_global_cb_manager)(struct gk20a *, + struct channel_gk20a *, bool); +void __gr_gm20b_op(commit_global_pagepool)(struct gk20a *, + struct channel_ctx_gk20a *, u64 , u32, bool); +int __gr_gm20b_op(handle_sw_method)(struct gk20a *, u32 , u32, u32, u32); +void __gr_gm20b_op(set_alpha_circular_buffer_size)(struct gk20a *, u32); +void __gr_gm20b_op(set_circular_buffer_size)(struct gk20a *, u32); +void __gr_gm20b_op(enable_hww_exceptions)(struct gk20a *); +bool __gr_gm20b_op(is_valid_class)(struct gk20a *, u32); +void __gr_gm20b_op(get_sm_dsm_perf_regs)(struct gk20a *, u32 *, u32 **, u32 *); +void __gr_gm20b_op(get_sm_dsm_perf_ctrl_regs)(struct gk20a *, + u32 *, u32 **, u32 *); +int __gr_gm20b_op(init_fs_state)(struct gk20a *); +void __gr_gm20b_op(set_hww_esr_report_mask)(struct gk20a *); +int __gr_gm20b_op(falcon_load_ucode)(struct gk20a *, + u64, struct gk20a_ctxsw_ucode_segments *, u32); +u32 __gr_gm20b_op(get_gpc_tpc_mask)(struct gk20a *, u32); +int __gr_gm20b_op(load_ctxsw_ucode)(struct gk20a *); + +#define __set_gr_gm20b_ops() \ + /* newly defined for gm20b */ \ + __set_gr_gm20b_op(init_gpc_mmu), \ + __set_gr_gm20b_op(bundle_cb_defaults), \ + __set_gr_gm20b_op(cb_size_default), \ + __set_gr_gm20b_op(calc_global_ctx_buffer_size), \ + __set_gr_gm20b_op(commit_global_bundle_cb), \ + __set_gr_gm20b_op(commit_global_cb_manager), \ + __set_gr_gm20b_op(commit_global_pagepool), \ + __set_gr_gm20b_op(handle_sw_method), \ + __set_gr_gm20b_op(set_alpha_circular_buffer_size), \ + __set_gr_gm20b_op(set_circular_buffer_size), \ + __set_gr_gm20b_op(enable_hww_exceptions), \ + __set_gr_gm20b_op(is_valid_class), \ + __set_gr_gm20b_op(get_sm_dsm_perf_regs), \ + __set_gr_gm20b_op(get_sm_dsm_perf_ctrl_regs), \ + __set_gr_gm20b_op(init_fs_state), \ + __set_gr_gm20b_op(set_hww_esr_report_mask), \ + __set_gr_gm20b_op(falcon_load_ucode), \ + __set_gr_gm20b_op(get_gpc_tpc_mask), \ + \ + /* reused from gk20a */ \ + __set_gr_gk20a_op(access_smpc_reg), \ + __set_gr_gk20a_op(commit_global_attrib_cb), \ + __set_gr_gk20a_op(free_channel_ctx), \ + __set_gr_gk20a_op(alloc_obj_ctx), \ + __set_gr_gk20a_op(free_obj_ctx), \ + __set_gr_gk20a_op(bind_ctxsw_zcull), \ + __set_gr_gk20a_op(get_zcull_info) + +#endif diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index a089b59c..2a888e88 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c @@ -388,24 +388,26 @@ static int gm20b_determine_L2_size_bytes(struct gk20a *g) return cache_size; } -void gm20b_init_ltc(struct gpu_ops *gops) -{ - /* Gk20a reused ops. */ - gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; - gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; - gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; - gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; - gops->ltc.init_cbc = gk20a_ltc_init_cbc; - - /* GM20b specific ops. */ - gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; - gops->ltc.init_comptags = gm20b_ltc_init_comptags; - gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; - gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; - gops->ltc.isr = gm20b_ltc_isr; - gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; - gops->ltc.flush = gm20b_flush_ltc; +static struct gpu_ltc_ops gm20b_ltc_ops = { + .determine_L2_size_bytes = gm20b_determine_L2_size_bytes, + .set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last, + .set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry, + .init_cbc = gk20a_ltc_init_cbc, #ifdef CONFIG_DEBUG_FS - gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; + .sync_debugfs = gk20a_ltc_sync_debugfs, #endif + /* GM20b specific ops. */ + .init_fs_state = gm20b_ltc_init_fs_state, + .init_comptags = gm20b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .elpg_flush = gm20b_ltc_g_elpg_flush_locked, + .isr = gm20b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc +}; + +void gm20b_init_ltc(struct gpu_ops *gops) +{ + gops->ltc = &gm20b_ltc_ops; } -- cgit v1.2.2