From 227c6f7b7a499dd58e0db6859736cfe586ef0897 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Aug 2018 14:09:36 -0700 Subject: gpu: nvgpu: Move fuse HAL to common Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1797177 --- drivers/gpu/nvgpu/gm20b/fuse_gm20b.c | 91 ------------------------------------ drivers/gpu/nvgpu/gm20b/fuse_gm20b.h | 37 --------------- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 7 ++- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 13 +++++- drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 5 +- 5 files changed, 16 insertions(+), 137 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gm20b/fuse_gm20b.c delete mode 100644 drivers/gpu/nvgpu/gm20b/fuse_gm20b.h (limited to 'drivers/gpu/nvgpu/gm20b') diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c deleted file mode 100644 index 95ac8ee3..00000000 --- a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * GM20B FUSE - * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "gk20a/gk20a.h" - -#include "fuse_gm20b.h" - -#include - -int gm20b_fuse_check_priv_security(struct gk20a *g) -{ - u32 gcplex_config; - - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel"); - return 0; - } - - if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { - nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); - return -EINVAL; - } - - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - - if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { - /* - * all falcons have to boot in LS mode and this needs - * wpr_enabled set to 1 and vpr_auto_fetch_disable - * set to 0. In this case gmmu tries to pull wpr - * and vpr settings from tegra mc - */ - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - if ((gcplex_config & - GCPLEX_CONFIG_WPR_ENABLED_MASK) && - !(gcplex_config & - GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { - if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) - nvgpu_log(g, gpu_dbg_info, - "gcplex_config = 0x%08x, " - "secure mode: ACR debug", - gcplex_config); - else - nvgpu_log(g, gpu_dbg_info, - "gcplex_config = 0x%08x, " - "secure mode: ACR non debug", - gcplex_config); - } else { - nvgpu_err(g, "gcplex_config = 0x%08x " - "invalid wpr_enabled/vpr_auto_fetch_disable " - "with priv_sec_en", gcplex_config); - /* do not try to boot GPU */ - return -EINVAL; - } - } else { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - nvgpu_log(g, gpu_dbg_info, - "gcplex_config = 0x%08x, non secure mode", - gcplex_config); - } - - return 0; -} diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h deleted file mode 100644 index 51734b2f..00000000 --- a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * GM20B FUSE - * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _NVGPU_GM20B_FUSE -#define _NVGPU_GM20B_FUSE - -#define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK ((u32)(1 << 0)) -#define GCPLEX_CONFIG_VPR_ENABLED_MASK ((u32)(1 << 1)) -#define GCPLEX_CONFIG_WPR_ENABLED_MASK ((u32)(1 << 2)) - - -struct gk20a; - -int gm20b_fuse_check_priv_security(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index abc39362..68ae91e8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -40,7 +40,6 @@ #include #include #include -#include #include void gr_gm20b_init_gpc_mmu(struct gk20a *g) @@ -549,7 +548,7 @@ u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) struct gr_gk20a *gr = &g->gr; /* Toggle the bits of NV_FUSE_STATUS_OPT_TPC_GPC */ - val = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(gpc_index)); + val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, gpc_index); return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); } @@ -1076,7 +1075,7 @@ u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) * flip the bits. * Also set unused bits to zero */ - fbp_en_mask = gk20a_readl(g, fuse_status_opt_fbp_r()); + fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g); fbp_en_mask = ~fbp_en_mask; fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1); @@ -1114,7 +1113,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) /* mask of Rop_L2 for each FBP */ for_each_set_bit(i, &fbp_en_mask, max_fbps_count) { - tmp = gk20a_readl(g, fuse_status_opt_rop_l2_fbp_r(i)); + tmp = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i); gr->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp; } diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 431cfc9b..acdf4591 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -32,6 +32,7 @@ #include "common/therm/therm_gm20b.h" #include "common/therm/therm_gm20b.h" #include "common/ltc/ltc_gm20b.h" +#include "common/fuse/fuse_gm20b.h" #include "gk20a/gk20a.h" #include "gk20a/ce2_gk20a.h" @@ -55,7 +56,6 @@ #include "regops_gm20b.h" #include "hal_gm20b.h" #include "acr_gm20b.h" -#include "fuse_gm20b.h" #include #include @@ -64,7 +64,6 @@ #include #include -#include #include #include #include @@ -649,6 +648,16 @@ static const struct gpu_ops gm20b_ops = { }, .fuse = { .check_priv_security = gm20b_fuse_check_priv_security, + .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, + .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, + .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, + .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, + .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, + .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, + .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, + .read_vin_cal_fuse_rev = NULL, + .read_vin_cal_slope_intercept_fuse = NULL, + .read_vin_cal_gain_offset_fuse = NULL, }, .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, .get_litter_value = gm20b_get_litter_value, diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 731078f7..53bec96f 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -36,7 +36,6 @@ #include #include -#include #define gm20b_dbg_pmu(g, fmt, arg...) \ nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) @@ -267,9 +266,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g) u32 val; nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", - gk20a_readl(g, fuse_opt_sec_debug_en_r())); + g->ops.fuse.fuse_opt_sec_debug_en(g)); nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", - gk20a_readl(g, fuse_opt_priv_sec_en_r())); + g->ops.fuse.fuse_opt_priv_sec_en(g)); nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); } -- cgit v1.2.2