From 2d0149c9abd74fd6bb59e076cfd46f49097e5662 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 23 Aug 2018 14:45:19 -0400 Subject: gpu: nvgpu: resolve MISRA 10.3 violations MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This value was then returned in a function defined by gpu_ops. This patch changes the return type for these gpu_ops to u64 and updates the functions that implement the functions and lastly the saved value. This removes the violation in this instance. JIRA NVGPU-647 Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1805588 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/regops_gm20b.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/regops_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h index f0246e0e..99044f09 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h @@ -2,7 +2,7 @@ * * Tegra GK20A GPU Debugger Driver Register Ops * - * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2018 NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,17 +28,17 @@ struct dbg_session_gk20a; const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void); -int gm20b_get_global_whitelist_ranges_count(void); +u64 gm20b_get_global_whitelist_ranges_count(void); const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void); -int gm20b_get_context_whitelist_ranges_count(void); +u64 gm20b_get_context_whitelist_ranges_count(void); const u32 *gm20b_get_runcontrol_whitelist(void); -int gm20b_get_runcontrol_whitelist_count(void); +u64 gm20b_get_runcontrol_whitelist_count(void); const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void); -int gm20b_get_runcontrol_whitelist_ranges_count(void); +u64 gm20b_get_runcontrol_whitelist_ranges_count(void); const u32 *gm20b_get_qctl_whitelist(void); -int gm20b_get_qctl_whitelist_count(void); +u64 gm20b_get_qctl_whitelist_count(void); const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void); -int gm20b_get_qctl_whitelist_ranges_count(void); +u64 gm20b_get_qctl_whitelist_ranges_count(void); int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); #endif /* __REGOPS_GM20B_H_ */ -- cgit v1.2.2