From ca762e42205febba72ce063417e1ac598610941d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 15 Mar 2017 14:08:32 -0700 Subject: gpu: nvgpu: Move all FB programming to FB HAL Move all programming of FB to fb_*.c files, and remove the inclusion of FB hardware headers from other files. TLB invalidate function took previously a pointer to VM, but the new API takes only a PDB mem_desc, because FB does not need to know about higher level VM. GPC MMU is programmed from the same function as FB MMU, so added dependency to GR hardware header to FB. GP106 ACR was also triggering a VPR fetch, but that's not applicable to dGPU, so removed that call. Change-Id: I4eb69377ac3745da205907626cf60948b7c5392a Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1321516 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 69 -------------------------------------- 1 file changed, 69 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/mm_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index cd1a106d..0b3192cc 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c @@ -22,75 +22,9 @@ #include #include -#include -#include #include #include -static int gm20b_mm_mmu_vpr_info_fetch_wait(struct gk20a *g, - unsigned int msec) -{ - struct nvgpu_timeout timeout; - - nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER); - - do { - u32 val; - - val = gk20a_readl(g, fb_mmu_vpr_info_r()); - if (fb_mmu_vpr_info_fetch_v(val) == - fb_mmu_vpr_info_fetch_false_v()) - return 0; - - } while (!nvgpu_timeout_expired(&timeout)); - - return -ETIMEDOUT; -} - -int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g) -{ - if (gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) { - return -ETIME; - } - - gk20a_writel(g, fb_mmu_vpr_info_r(), - fb_mmu_vpr_info_fetch_true_v()); - - return gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); -} - -static bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g) -{ - u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); - return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) == - gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); -} - -static void gm20b_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) -{ - u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; - - if (enable) { - fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); - gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); - g->mmu_debug_ctrl = true; - } else { - fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); - gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); - g->mmu_debug_ctrl = false; - } - - reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); - reg_val = set_field(reg_val, - fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); - gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); - - reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); - reg_val = set_field(reg_val, - gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); - gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); -} - static void gm20b_mm_set_big_page_size(struct gk20a *g, struct mem_desc *mem, int size) { @@ -157,8 +91,6 @@ static bool gm20b_mm_is_bar1_supported(struct gk20a *g) void gm20b_init_mm(struct gpu_ops *gops) { gops->mm.support_sparse = gm20b_mm_support_sparse; - gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled; - gops->mm.set_debug_mode = gm20b_mm_mmu_set_debug_mode; gops->mm.gmmu_map = gk20a_locked_gmmu_map; gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; gops->mm.vm_remove = gk20a_vm_remove_support; @@ -168,7 +100,6 @@ void gm20b_init_mm(struct gpu_ops *gops) gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; gops->mm.l2_flush = gk20a_mm_l2_flush; gops->mm.cbc_clean = gk20a_mm_cbc_clean; - gops->mm.tlb_invalidate = gk20a_mm_tlb_invalidate; gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; gops->mm.get_iova_addr = gk20a_mm_iova_addr; -- cgit v1.2.2