From 1c9aaa1eafcf91fbc29404b449f2bec072c804a5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 25 Apr 2014 15:00:54 +0300 Subject: gpu: nvgpu: Implement ELPG flush for gm20b ELPG flush is initiated from a common broadcast register, but must be waited on via per-L2 registers. Split gk20a and gm20b versions of the flush. Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/401545 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h index 28c58f50..9840805d 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h @@ -96,11 +96,11 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) { - return 0x1; + return 0x1; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) { - return 0x2; + return 0x2; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) { @@ -258,6 +258,22 @@ static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) { return 0x1; } +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} static inline u32 ltc_ltc0_ltss_intr_r(void) { return 0x0014020c; -- cgit v1.2.2