From ea5a2147229e32f0524827af82cb7a880aca6296 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 14 Dec 2016 14:43:42 -0800 Subject: gpu: nvgpu: Implement SET_RD_COALESCE Implement SW method SET_RD_COALESCE to implement correct handling of texture read coalescing. Bug 200223870 Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1271303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 68b5a6d4..9f7fea45 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -2254,6 +2254,18 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) { return 0x005030f8; } +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) +{ + return 0x00419a3c; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) +{ + return 0x1 << 2; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; -- cgit v1.2.2