From 8ec63298789a0912b9cbd90ee47c76f0701f0dca Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 16 Nov 2015 16:30:28 -0800 Subject: gpu: nvgpu: correct register setting for debug mode correct register settings for both set mmu debug mode and set sm debug mode. JIRA VFND-1005 Bug 1594604 Change-Id: I1d4b1d4b4cdd9d24d3b00481e0e22c4217f5a4b3 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/833490 Reviewed-by: Aingara Paramakuru Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index d91d40af..a941eb59 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h @@ -3070,6 +3070,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) { return 0x00504610; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) { return (r >> 0) & 0x1; @@ -3078,6 +3082,18 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3090,6 +3106,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) +{ + return 0x1 << 1; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) { return (r >> 1) & 0x1; @@ -3098,6 +3118,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) +{ + return 0x1 << 2; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) { return (r >> 2) & 0x1; -- cgit v1.2.2