From 211edaefb71d06d34c2835a93249da58673bff8a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 May 2016 15:13:54 -0700 Subject: gpu: nvgpu: Fix CWD floorsweep programming Program CWD TPC and SM registers correctly. The old code did not work when there are more than 4 TPCs. Refactor init_fs_mask to reduce code duplication. Change-Id: Id93c1f8df24f1b7ee60314c3204e288b91951a88 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1143697 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 73861c07..45240e97 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h @@ -1962,10 +1962,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) { return 0x00405b60 + i*4; } +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) { return (v & 0xf) << 0; } +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) { return (v & 0xf) << 8; @@ -1974,6 +1986,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i) { return 0x00405ba0 + i*4; } +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000006; +} static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) { return (v & 0xff) << 0; -- cgit v1.2.2