From ec62c649b5338e7608ea82546135e88f443b90a8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 19 Apr 2016 10:27:11 -0700 Subject: gpu: nvgpu: Idle GR before calling PMU ZBC save On gk20a when PMU is updating ZBC colors it is reading them from L2. But L2 has one port, and ZBC reads can race with other transactions. Idle graphics before sending PMU the ZBC_UPDATE request. Also makes pmu_save_zbc a HAL, because PMU ucode has changes to bypass this problem on some chips. Bug 1746047 Change-Id: Id8fcd6850af7ef1d8f0a6aafa0fe6b4f88b5f2d9 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1129017 --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 40925f48..5b00078f 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1372,6 +1372,8 @@ void gm20b_init_gr(struct gpu_ops *gops) gops->gr.add_zbc_depth = gr_gk20a_add_zbc_depth; gops->gr.zbc_set_table = gk20a_gr_zbc_set_table; gops->gr.zbc_query_table = gr_gk20a_query_zbc; + gops->gr.pmu_save_zbc = gk20a_pmu_save_zbc; + gops->gr.add_zbc = gr_gk20a_add_zbc; gops->gr.pagepool_default_size = gr_gm20b_pagepool_default_size; gops->gr.init_ctx_state = gr_gk20a_init_ctx_state; gops->gr.alloc_gr_ctx = gr_gm20b_alloc_gr_ctx; -- cgit v1.2.2