From e7664f9345772de177fbe20cf415d2fbc6f55d83 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 26 Feb 2016 11:33:08 -0800 Subject: gpu: nvgpu: make tpc_fs_mask work on production board On production fused boards, it uses gr_fe_tpc_fs_r() to mask TPCs, rather than fues. Bug 1734150 Change-Id: I7b4eb428f1ad0cf841a57214e0c8c1e8f17b2c5a Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1111630 (cherry picked from commit 869ea54967812e03d9f1e69775ca56fd6459216c) Reviewed-on: http://git-master/r/1122121 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 6a79b1ac..050c2bee 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -592,7 +592,14 @@ int gr_gm20b_ctx_state_floorsweep(struct gk20a *g) for (pes_index = 0; pes_index < gr->pe_count_per_gpc; pes_index++) pes_tpc_mask |= gr->pes_tpc_mask[pes_index][gpc_index]; - gk20a_writel(g, gr_fe_tpc_fs_r(), pes_tpc_mask); + if (g->tpc_fs_mask_user && g->ops.gr.get_gpc_tpc_mask(g, 0) == + (0x1 << gr->max_tpc_count) - 1) { + u32 val = g->tpc_fs_mask_user; + val &= (0x1 << gr->max_tpc_count) - 1; + gk20a_writel(g, gr_fe_tpc_fs_r(), val); + } else { + gk20a_writel(g, gr_fe_tpc_fs_r(), pes_tpc_mask); + } for (tpc_index = 0; tpc_index < gr->tpc_count; tpc_index++) { if (tpc_index == 0) { -- cgit v1.2.2