From dc281d6a9ebadaeb66dab092b40b7d6f4559ee39 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 17:19:51 -0700 Subject: gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU debug mode for a given context. Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL for a given channel. HAL implementation for native case is gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly writes to the register if the context is resident, or writes to gr context otherwise. Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature. NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode, so the feature is only enabled on TU104 for now. Bug 2515097 But 2713590 Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2110720 (cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767 Reviewed-by: Kajetan Dutka Reviewed-by: Alex Waterman Reviewed-by: Winnie Hsu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c67f7870..d00181af 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B GPC MMU * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,6 +33,7 @@ #include #include "gk20a/gr_gk20a.h" +#include "gk20a/regops_gk20a.h" #include "gr_gm20b.h" #include "pmu_gm20b.h" @@ -1455,6 +1456,26 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); } +int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, bool enable) +{ + struct nvgpu_dbg_reg_op ctx_ops = { + .op = REGOP(WRITE_32), + .type = REGOP(TYPE_GR_CTX), + .offset = gr_gpcs_pri_mmu_debug_ctrl_r(), + .value_lo = enable ? + gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() : + gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(), + }; + int err; + + err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL); + if (err != 0) { + nvgpu_err(g, "Failed to access register"); + } + return err; +} + void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) { u32 reg_val, gpc_debug_ctrl; -- cgit v1.2.2