From d8c0144f8b45ef8a94fc696efaa0c782c4c787af Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 13:43:35 -0700 Subject: gpu: nvgpu: add clear_sm_hww gr ops Required for multiple SM support and t19x SM register address changes JIRA GPUT19X-75 Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 333f0340..90046232 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1530,6 +1530,18 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, priv_addr_table, priv_addr_table_index); } +static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr) +{ + u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); + + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, + global_esr); + + /* clear the warp hww */ + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); +} + void gm20b_init_gr(struct gpu_ops *gops) { gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; @@ -1640,4 +1652,5 @@ void gm20b_init_gr(struct gpu_ops *gops) gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; gops->gr.lock_down_sm = gk20a_gr_lock_down_sm; gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down; + gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww; } -- cgit v1.2.2