From 8a76e8b4910480efcdeb47d18cb209e247d9eda8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 16 Aug 2018 14:05:02 -0700 Subject: gpu: nvgpu: Split HUB and GPC MMU debug mode set HUB and GPC MMU debug modes were set in the same function. This introduced a dependency from FB code to GR registers. Split setting of GPC MMU debug mode to GR HAL. Change-Id: I003446f9dfa147f526bd01d3b6130f4037d9b183 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1801420 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 7ed36144..101f4211 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1516,3 +1516,19 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) { return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); } + +void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) +{ + u32 reg_val, gpc_debug_ctrl; + + if (enable) { + gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); + } else { + gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); + } + + reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); + reg_val = set_field(reg_val, + gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); + gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); +} -- cgit v1.2.2