From 6a46965eb3b7b657c089142579ab20d6efefc0fc Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 6 Jun 2018 20:46:03 -0700 Subject: gpu: nvgpu: correct calculation of sm_id for .record_sm_error_state Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 331c3af9..261c3054 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1278,7 +1278,7 @@ void gr_gm20b_get_access_map(struct gk20a *g, *num_entries = ARRAY_SIZE(wl_addr_gm20b); } -int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, +int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, struct channel_gk20a *fault_ch) { int sm_id; @@ -1306,7 +1306,7 @@ int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, nvgpu_mutex_release(&g->dbg_sessions_lock); - return 0; + return sm_id; } int gm20b_gr_update_sm_error_state(struct gk20a *g, -- cgit v1.2.2