From 227c6f7b7a499dd58e0db6859736cfe586ef0897 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Aug 2018 14:09:36 -0700 Subject: gpu: nvgpu: Move fuse HAL to common Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1797177 --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index abc39362..68ae91e8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -40,7 +40,6 @@ #include #include #include -#include #include void gr_gm20b_init_gpc_mmu(struct gk20a *g) @@ -549,7 +548,7 @@ u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) struct gr_gk20a *gr = &g->gr; /* Toggle the bits of NV_FUSE_STATUS_OPT_TPC_GPC */ - val = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(gpc_index)); + val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, gpc_index); return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); } @@ -1076,7 +1075,7 @@ u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) * flip the bits. * Also set unused bits to zero */ - fbp_en_mask = gk20a_readl(g, fuse_status_opt_fbp_r()); + fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g); fbp_en_mask = ~fbp_en_mask; fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1); @@ -1114,7 +1113,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) /* mask of Rop_L2 for each FBP */ for_each_set_bit(i, &fbp_en_mask, max_fbps_count) { - tmp = gk20a_readl(g, fuse_status_opt_rop_l2_fbp_r(i)); + tmp = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i); gr->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp; } -- cgit v1.2.2